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| CXD3003R CD Digital Signal Processor with Built-in Digital Servo and DAC For the availability of this product, please contact the sales office. Description The CXD3003R is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, digital filter and 1-bit DAC. Features * All digital signal processing during playback is performed with a single chip * Highly integrated mounting possible due to a builtin RAM Digital Signal Processor (DSP) Block * Playback mode supporting CAV (Constant Angular Velocity) * Frame jitter free * 0.5x to 24x continuous playback possible with a low external clock * Allows relative rotational velocity readout * Wide capture range playback mode * Spindle rotational velocity following method * Supports 1x to 24x playback by switching the builtin VCO * The bit clock, which strobes the EFM signal, is generated by the digital PLL * EFM data demodulation * Enhanced EFM frame sync signal protection * Refined super strategy-based powerful error correction C1: double correction, C2: quadruple correction Supported during 24x playback * Noise reduction during track jumps * Auto zero-cross mute * Subcode demodulation and Sub Q data error detection * Digital spindle servo (built-in oversampling filter) * 16-bit traverse counter * Asymmetry compensation circuit * CPU interface on serial bus * Error correction monitor signal, etc. output from a new CPU interface * Servo auto sequencer * Fine search performs track jumps with high accuracy * Digital audio interface outputs * Digital level meter, peak meter * Bilingual compatible * VCO control mode Digital Servo (DSSP) Block * Microcomputer software-based flexible servo control * Offset cancel function for servo error signal * Auto gain control function for servo loop * E:F balance, focus bias adjustment function * Surf jump function supporting micro two-axis Digital Filter and DAC Blocks * Digital de-emphasis * Digital attenuation * 4Fs oversampling filter * Adoption of a secondary noise shaper * Supports double-speed playback Structure Silicon gate CMOS IC Absolute Maximum Ratings * Supply voltage VDD -0.3 to +4.6 V * Input voltage VI -0.3 to +4.6 V (VSS - 0.3V to VDD + 0.3V) * Output voltage VO -0.3 to +4.6 V * Storage temperature Tstg -40 to +125 C * Supply voltage difference VSS - AVSS -0.3 to +0.3 V V VDD - AVDD -0.3 to +0.3 Recommended Operating Conditions * Supply voltage VDD 3.0 to 4.0 V * Operating temperature Topr -20 to +75 C The VDD (min.) for the CXD3003R varies according to the playback speed and built-in VCO selection. The VDD (min.) for the CXD3003R under various conditions are as shown on the following page. 144 pin LQFP (Plastic) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E97306A88 CXD3003R Maximum Operating Speed 24 23 +25C 22 21 +55C [Multiple] 20 +75C 19 18 17 16 15 3.0 3.1 3.2 3.3 3.4 3.5 [V] 3.6 3.7 3.8 3.9 4.0 The maximum operating speed graph shows the playback speed VDD (min.) at various temperatures. The playback conditions are middle-speed VCO1 and high-speed VCO2 selected in CAV-W mode with DSPB = 1. -2- CXD3003R Block Diagram VPCO1 VPCO2 PCMDI XTLO DTS1 DTS2 XTSL DAS0 BCKI LRCKI XTLI DAS1 XWO 86 87 6 7 51 75 70 77 78 79 28 30 26 DAC Block MCKO 52 V16M 135 VCKI 134 FSTO 55 C4M 56 C16M 57 VCTL 8 PDO 133 VCOI 129 VCOO 128 PCO 11 FILI 10 FILO 9 CLTV 12 RFAC 14 ASYI 16 ASYO 17 ASYE 22 WFCK 62 SCOR 63 EXCK 65 SBSO 64 SQCK 67 SQSO 66 MON 114 FSW 113 MDP 115 MDS 116 CLV processor Timing Generator1 Subcode P to W processor Digital out Subcode Q processor Error corrector CPU interface Peak detector MUX Sync protector D/A data processor Digital PLL Vari-Pitch double speed EFM Demodulator OSC 32K RAM Clock Generator 4fs Digital Filter + 1 bit DAC 91 AO1F 92 AO1R 83 AO2F 82 AO2R Register Address generator 8 Priority encoder Serial/parallel processor 23 PSSL 49 to 44, DA01 42 to 31, 29, 27 to DA16 61 MUTE 60 DOUT 59 MD2 99 DATA 101 CLOK 100 XLAT Noise Shaper PWMI 112 18-times oversampling filter Timing Generator 2 Servo auto sequencer 95 SENS Signal Processor Block Servo Block MIRR DFCT FOK Servo Interface 103 COUT 104 MIRR 105 DFCT 106 FOK PWM GENERATOR 120 SFDR 121 SRDR 122 TFDR 123 TRDR 124 FFDR 125 FRDR RFDC 140 CE 141 TE 142 SE 3 FE 4 VC 5 OpAmp AnaSw A/D CONVERTER SERVO DSP FOCUS SERVO TRACKING SERVO SLED SERVO FOCUS PWM GENERATOR TRACKING PWM GENERATOR SLED PWM GENERATOR 139 130 131 132 20 18 136 21 13 138 69 DVDD1 AVDD2 DVDD0 AVDD4 AVSS2 AVDD3 AVSS3 AVDD5 DVSS0 DVSS1 -3- AVDD1 AVSS1 AVSS4 AVSS5 XRST TEST TES2 TES3 ADIO CXD3003R Pin Configuration DVDD4 AVDD3 AVDD5 AVDD4 DVSS4 AVSS3 AVSS5 AVSS4 COUT AO2R DVSS3 CLOK SENS AO1R DFCT AO1F DATA SCLK ATSK AO2F DAS0 XTLO DAS1 DTS0 MIRR XTLI DTS1 XLAT DIRC NC NC XWO FOK 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 NC 109 NC 110 TESTA 111 PWMI 112 FSW 113 MON 114 MDP 115 MDS 116 LOCK 117 SSTP 118 DVSS5 119 SFDR 120 SRDR 121 TFDR 122 TRDR 123 FFDR 124 FRDR 125 DVDD5 126 NC 127 VCOO 128 VCOI 129 TEST 130 TES2 131 TES3 132 PDO 133 VCKI 134 V16M 135 AVDD2 136 IGEN 137 AVSS2 138 ADIO 139 RFDC 140 CE 141 TE 142 NC 143 NC 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72 NC 71 NC 70 DTS2 69 XRST 68 SCSY 67 SQCK 66 SQSO 65 64 EXCK SBSO NC NC NC 63 SCOR 62 WFCK 61 MUTE 60 DOUT 59 58 MD2 DVDD3 57 C16M 56 C4M 55 FSTO 54 NC 53 FSTI 52 MCKO 51 XTSL 50 DVSS2 49 DA01 48 47 46 45 44 DA02 DA03 DA04 DA05 DA06 43 DVDD2 42 DA07 41 DA08 40 DA09 39 DA10 38 NC 37 NC NC NC AVSS1 LRCK ASYI VPCO1 VPCO2 WDCK CLTV RFAC VCTL PSSL DA14 PCMDI AVDD1 ASYE DVSS1 ASYO DA16 DA15 -4- DVDD1 LRCKI DA13 DA12 DA11 NC BCKI FILO BIAS VC FILI PCO NC NC SE FE CXD3003R Pin Description Pin No. 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 39 40 Symbol SE FE VC VPCO1 VPCO2 VCTL FILO FILI PCO CLTV AVSS1 RFAC BIAS ASYI ASYO AVDD1 DVDD1 DVSS1 ASYE PSSL WDCK LRCK LRCKI DA16 PCMDI DA15 BCKI DA14 DA13 DA12 DA11 DA10 DA09 I I O O I O I O I O O O O O O 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 I I I O 1, 0 I I I O O I O I O I 1, Z, 0 Analog 1, Z, 0 1, Z, 0 I/O Sled error signal input. Focus error signal input. Center voltage input. Wide-band EFM PLL VCO2 charge pump output. Wide-band EFM PLL VCO2 charge pump output 2. Turned on and off by $E command FCSW. Wide-band EFM PLL VCO2 control voltage input. Master PLL filter output (slave = digital PLL). Master PLL filter input. Master PLL charge pump output. Multiplier VCO control voltage input. Analog GND. EFM signal input. Asymmetry circuit constant current input. Asymmetry comparator voltage input. EFM full-swing output (low = VSS, high = VDD). Analog power supply. Digital power supply. Digital GND. Asymmetry circuit on/off (low = off, high = on). Audio data output mode switching input (low: serial, high: parallel). D/A interface for 48-bit slot. Word clock f = 2Fs. D/A interface for 48-bit slot. LR clock f = Fs. LR clock input to DAC (48-bit slot). DA16 (MSB) output when PSSL = 1, 48-bit slot serial data output (two's complement, MSB first) when PSSL = 0. Audio data input to DAC (48-bit slot). DA15 output when PSSL = 1, 48-bit slot bit clock output when PSSL = 0. Bit clock input to DAC (48-bit slot). DA14 output when PSSL = 1, 64-bit slot serial data output (two's complement, LSB first) when PSSL = 0. DA13 output when PSSL = 1, 64-bit slot bit clock output when PSSL = 0. DA12 output when PSSL = 1, 64-bit slot LR clock output when PSSL = 0. DA11 output when PSSL = 1, GTOP output when PSSL = 0. DA10 output when PSSL = 1, XUGF output when PSSL = 0. DA09 output when PSSL = 1, XPLCK output when PSSL = 0. Description -5- CXD3003R Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 75 76 77 78 79 80 81 82 Symbol DA08 DA07 DVDD2 DA06 DA05 DA04 DA03 DA02 DA01 DVSS2 XTSL MCKO FSTI FSTO C4M C16M DVDD3 MD2 DOUT MUTE WFCK SCOR SBSO EXCK SQSO SQCK SCSY XRST DTS2 DTS1 DTS0 XWO DAS0 DAS1 DVSS3 AVSS4 AO2R O I O I O O O I O I I I I I I I I I I O I O O O O O O O O O O O I/O 1, 0 1, 0 Description DA08 output when PSSL = 1, GFS output when PSSL = 0. DA07 output when PSSL = 1, RFCK output when PSSL = 0. Digital power supply. 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 DA06 output when PSSL = 1, C2PO output when PSSL = 0. DA05 output when PSSL = 1, XRAOF output when PSSL = 0. DA04 output when PSSL = 1, MNT3 output when PSSL = 0. DA03 output when PSSL = 1, MNT2 output when PSSL = 0. DA02 output when PSSL = 1, MNT1 output when PSSL = 0. DA01 output when PSSL = 1, MNT0 output when PSSL = 0. Digital GND. Crystal selection input. 1, 0 Clock output. Inverted output of XTLI. 2/3 frequency division input for XTLI pin. 1, 0 1, 0 1, 0 2/3 frequency division output for XTLI pin. Does not change with variable pitch. 1/4 frequency division output for XTLI pin. Changes with variable pitch. 16.9344MHz output. Changes simultaneously with variable pitch. Digital power supply. Digital Out on/off control (low = off, high = on). 1, 0 Digital Out output. Mute (low: off, high: on). 1, 0 1, 0 1, 0 WFCK (Write Frame Clock) output. Outputs a high signal when either subcode sync S0 or S1 is detected. Sub P to W serial output. SBSO readout clock input. 1, 0 Sub Q 80-bit and PCM peak and level data 16-bit output. SQSO readout clock input. GRSCOR re-synchronization input. Normally low, re-syncronization is executed when high. System reset. Reset when low. DAC test pin. Normally fixed to high. DAC test pin. Normally fixed to high. DAC test pin. Normally fixed to low. DAC sync window open input. Normally high, window open when low. DAC test pin. Normally fixed to high. DAC test pin. Normally fixed to low. Digital GND. Analog GND. 1, Z, 0 Channel 2 DAC PWM output (reversed phase). -6- CXD3003R Pin No. 83 84 85 86 87 88 89 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 111 112 113 114 115 116 117 118 119 120 121 122 Symbol AO2F AVDD4 AVDD5 XTLO XTLI AVSS5 AVSS3 AO1F AO1R AVDD3 AVDD4 SENS DIRC SCLK ATSK DATA XLAT CLOK DVSS4 COUT MIRR DFCT FOK TESTA PWMI FSW MON MDP MDS LOCK SSTP DVSS5 SFDR SRDR TFDR O O O I O O O O I/O I I/O I/O I/O I/O O I I I I I I O O O I O I/O 1, Z, 0 Description Channel 2 DAC PWM output (forward phase). Analog power supply. Master clock power supply. 1, 0 Master clock crystal oscillation circuit output. Master clock crystal oscillation circuit input. Master clock GND. Analog GND. 1, Z, 0 1, Z, 0 Channel 1 DAC PWM output (forward phase). Channel 1 DAC PWM output (reversed phase). Analog power supply. Digital power supply. 1, Z, 0 SENS output to CPU. Used during 1-track jumps. SENS serial data readout clock input. Anti-shock pin. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. Digital GND. 1, 0 1, 0 1, 0 1, 0 Track count signal I/O. Mirror signal I/O. Defect signal I/O. Focus OK signal I/O. Test pin. Leave this open. Spindle motor external pin input. 1, Z, 0 1, 0 1, Z, 0 1, Z, 0 1, 0 Spindle motor output filter switching output. GRSCOR output when $8 command SCOR SEL = high. Spindle motor on/off control output. Spindle motor servo control output. Spindle motor servo control output. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. Input when LKIN = high. Disc innermost track detection signal input. Digital GND. 1, 0 1, 0 1, 0 Sled drive output. Sled drive output. Tracking drive output. -7- CXD3003R Pin No. 123 124 125 126 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 Symbol TRDR FFDR FRDR DVDD5 VCOO VCOI TEST TES2 TES3 PDO VCKI V16M AVDD2 IGEN AVSS2 ADIO RFDC CE TE O I I I I O I I I I O I O O O O I/O 1, 0 1, 0 1, 0 Tracking drive output. Focus drive output. Focus drive output. Digital power supply. 1, 0 Description Analog EFM PLL oscillation circuit output. Analog EFM PLL oscillation circuit input. flock = 8.6436MHz Test pin. Normally fixed to low. Test pin. Normally fixed to low. Test pin. Normally fixed to low. 1, Z, 0 Analog EFM PLL charge pump output. Variable pitch clock input from the external VCO. fcenter = 16.9344MHz Set VCKI to low when the external clock is not input to this pin. 1, Z, 0 Wide-band EFM PLL VCO2 oscillation output. Analog power supply. Connects the operational amplifier current source reference resistance connection. Analog GND. Operational amplifier output. RF signal input. Center servo analog input. Tracking error signal input. In the CXD3003R, the following pins are NC. Pins 1, 2, 19, 35, 36, 37, 38, 54, 71, 72, 73, 74, 90, 107, 108, 109, 110, 127, 143 and 144 Notes) * The 64-bit slot is an LSB first, two's complement output. The 48-bit slot is an MSB first, two's complement output. * GTOP is used to monitor the frame sync protection status. (High: sync protection window released.) * XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync protection. * XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. * The GFS signal goes high when the frame sync and the insertion protection timing match. * RFCK is derived from the crystal accuracy, and has a cycle of 136s. * C2PO represents the data error status. * XRAOF is generated when the 32K RAM exceeds the 28F jitter margin. -8- CXD3003R Electrical Characteristics 1. DC Characteristics Item Input voltage (1) High level input voltage Low level input voltage High level input voltage Low level input voltage High level input voltage Low level input voltage High level input voltage Low level input voltage Input voltage Input voltage (VDD = AVDD = 3.3V 10%, VSS = AVSS = 0V, Topr = -20 to +75C) Conditions VIH (1) VIL (1) VIH (2) VIL (2) VIH (3) VIL (3) VIH (4) VIL (4) VIN (5) VIN (6) Schmitt input VI 5.5V VI 5.5V Schmitt input Analog input Analog input 0.7VDD 0.2VDD 0.7VDD 0.2VDD 0.7VDD 0.2VDD VSS VSS VDD - 0.4 0 VDD - 0.4 0 VDD - 0.2 0 0 VDD VDD VDD 0.4 VDD 0.4 VDD 0.4 0.4 VDD 0.4 10 20 5 Min. 0.7VDD 0.2VDD Typ. Max. Unit Applicable pins V V V V V V V V V V V V V V V V V V V A A A 3, 4, 5 6 10 7, 10 12 7, 10 12 8 11 5 6 9 4 3 2 1, 12 Input voltage (2) Input voltage (3) Input voltage (4) Input voltage (5) Input voltage (6) Output voltage (1) High level output voltage VOH (1) IOH = -8mA Low level output voltage VOL (1) IOL = 8mA High level output voltage VOH (2) IOH = -4mA Low level output voltage VOL (2) IOL = 4mA High level output voltage VOH (3) IOH = -2mA Low level output voltage VOL (3) IOL = 4mA Output voltage (2) Output voltage (3) Output voltage (4) Low level output voltage VOL (4) IOL = 4mA Output voltage (5) High level output voltage VOH (5) IOH = -0.28mA VDD - 0.5 Low level output voltage VOL (5) IOH = 0.36mA ILI (1) ILI (2) ILO VI = 0 to 5.5V VI = 0.25VDD to 0.75VDD VO = 0 to 3.6V 0 -10 -20 -5 Input leak current (1) Input leak current (2) Tri-state pin output leak current Applicable pins 1 BCKI, DTS0, DTS1, DTS2, LRCKI, PCMDI, TES2, TES3, TEST 2 ASYE, FSTI, VCKI 3 ATSK, DATA, DIRC, MD2, PWMI, SSTP, XLAT, XTSL, XWO 4 CLOK, EXCK, MUTE, SCLK, SCSY, SQCK, XRST 5 ASYI, BIAS, CLTV, FILI, IGEN, RFAC, VCTL 6 CE, FE, SE, TE, VC, RFDC 7 ASYO, C16M, C4M, DA01 to DA16, DAS0, DAS1, DOUT, FFDR, FRDR, FSTO, LRCK, MON, PSSL, SBSO, SCOR, SFDR, SQSO, SRDR, TFDR, TRDR, WDCK, WFCK 8 FSW 9 MCKO 10 AO1F, AO1R, AO2F, AO2R, MDP, MDS, PCO, PDO, SENS, V16M, VPCO1, VPCO2 11 FILO 12 COUT, DFCT, FOK, LOCK, MIRR -9- CXD3003R 2. AC Characteristics (1) XTLI pin, VCOI pin (a) When using self-excited oscillation (Topr = -20 to +75C, VDD = AVDD = 3.3V 10%) Item Oscillation frequency Symbol fMAX Min. 7 Typ. Max. 34 Unit MHz (b) When inputting pulses to XTLI and VCOI pins (Topr = -20 to +75C, VDD = AVDD = 3.3V 10%) Item High level pulse width Low level pulse width Pulse cycle Input high level Input low level Rise time, fall time Symbol Min. 13 13 26 VDD - 1.0 0.8 10 Typ. Max. 500 500 1000 Unit ns ns ns V V ns tWHX tWLX tCX VIHX VILX tR, tF tCX tWHX tWLX VIHX VIHX x 0.9 XTLI VDD/2 VIHX x 0.1 VILX tR tF (c) When inputting sine waves to XTLI and VCOI pins via a capacitor (Topr = -20 to +75C, VDD = AVDD = 3.3V 10%) Item Input amplitude Symbol VI Min. 2.0 Typ. Max. unit VDD + 0.3 Vp-p - 10 - CXD3003R (2) CLOK, DATA, XLAT, SQCK and EXCK pins (VDD = AVDD = 3.3V 10%, VSS = AVSS = 0V, Topr = -20 to +75C) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK SQCK frequency EXCK SQCK pulse width CNIN frequency CNIN pulse width Symbol fCK Min. Typ. Max. 16 30 30 30 30 750 0.65 750 65 7.5 Unit MHz ns ns ns ns ns MHz ns kHz s tWCK tSU tH tD tWL fT tWT fT tWT Only when $44 and $45 are executed. 1/fCK tWCK tWCK CLOK DATA XLAT tSU tH tD tWL EXCK SQCK CNIN tWT 1/fT tWT SBSO SQSO tSU tH - 11 - CXD3003R (3) SCLK pin XLAT tDLS tSPW SCLK 1/fSCLK Serial Read Out Data (SENS) *** MSB *** LSB Item SCLK frequency SCLK pulse width Delay time Symbol fSCLK Min. Typ. Max. 16 Unit MHz ns s tSPW tDLS 31.3 15 (4) COUT, MIRR and DFCT pins Operating frequency (VDD = AVDD = 3.3V 10%, VSS = AVSS = 0V, Topr = -20 to +75C) Item COUT maximum operating frequency MIRR maximum operating frequency DFCT maximum operating frequency Symbol Min. Typ. Max. Unit fCOUT fMIRR fDFCTH 40 40 5 kHz kHz kHz Conditions 1 2 3 1 When using a high-speed traverse TZC. 2 B A When the RF signal continuously satisfies the following conditions during the above traverse. * A = 0.11VDD to 0.23VDD * B 25% A+B 3 During complete RF signal omission. When settings related to DFCT signal generation are Typ. - 12 - CXD3003R (5) BCKI, LRCKI and PCMDI pins Item Input BCKI frequency Input BCKI pulse width Input data setup time Input data hold time Input LRCK setup time Input LRCK hold time (VDD = 3.3V 10%, Topr = -20 to +75C) Min. Typ. Max. 4.5 100 10 15 10 15 tWIB tWIB Symbol Unit MHz tBCK tWIB tIDS tIDH tILRH tILRS ns BCKI 50% tIDS tIDH PCMDI tILRH tILRS LRCKI - 13 - CXD3003R DAC Analog Characteristics Measurement conditions (Ta = 25C, VDD = 3.3V, Fs = 44.1kHz, signal frequency = 1kHz, measurement band = 4Hz to 20kHz, master clock = 768Fs) Item S/N ratio THD + N Dynamic range Channel separation Output level Difference in gain between channels 1 Using "A" weighting filter 2 -60 dB, 1kHz input Typ. 93 0.015 91 91 1.7 0.1 Unit dB % dB dB V (rms) dB Remarks (EIAJ) 1 (EIAJ) (EIAJ) 1, 2 (EIAJ) The analog characteristics measurement circuit is shown below. 820p CXD3003R 3.9k 130k AO1F 3.9k 47p 4.7k 4.7k 4.7k 3.9k 130k AO1R 3.9k 47p 820p 4.7k 0.015 4.7k 4.7k 1800p 4.7k 82p 22 100 OUTPUT 12k 768fs AO1F AO1R TEST DISK DATA CXD3003R AO2F AO2R Audio Circuit 2ch Analog 1ch SHIBASOKU (AM51A) Audio Analyzer Block diagram of analog characteristics measurement - 14 - CXD3003R Contents [1] CPU Interface 1-1. CPU Interface Timing ........................................................................................................................ 16 1-2. CPU Interface Command Table ........................................................................................................ 16 1-3. CPU Command Presets .................................................................................................................... 26 1-4. Description of SENS Signals ............................................................................................................. 31 [2] Subcode Interface 2-1. P to W Subcode Readout .................................................................................................................. 65 2-2. 80-bit Sub Q Readout ........................................................................................................................ 65 [3] Description of Modes 3-1. CLV-N Mode ...................................................................................................................................... 71 3-2. CLV-W Mode ..................................................................................................................................... 71 3-3. CAV-W Mode ..................................................................................................................................... 71 3-4. VCO-C Mode ..................................................................................................................................... 72 [4] Description of Other Functions 4-1. Channel Clock Regeneration by the Digital PLL Circuit .................................................................... 74 4-2. Frame Sync Protection ...................................................................................................................... 76 4-3. Error Correction ................................................................................................................................. 76 4-4. DA Interface ....................................................................................................................................... 77 4-5. Digital Out .......................................................................................................................................... 80 4-6. Servo Auto Sequence ....................................................................................................................... 81 4-7. Digital CLV ......................................................................................................................................... 89 4-8. Playback Speed ................................................................................................................................ 90 4-9. DAC Block Playback Speed .............................................................................................................. 91 4-10. DAC Block Input Timing .................................................................................................................... 91 4-11. Asymmetry Compensation ................................................................................................................ 92 4-12. CXD3003 Clock System .................................................................................................................... 93 [5] Description of Servo Signal Processing System Functions and Commands 5-1. General Description of the Servo Signal Processing System ............................................................ 94 5-2. Digital Servo Block Master Clock (MCK) ........................................................................................... 95 5-3. AVRG Measurement and Compensation .......................................................................................... 95 5-4. E:F Balance Adjustment Function ..................................................................................................... 97 5-5. FCS Bias Adjustment Function .......................................................................................................... 97 5-6. AGCNTL Function ............................................................................................................................. 99 5-7. FCS Servo and FCS Search ........................................................................................................... 101 5-8. TRK and SLD Servo Control ........................................................................................................... 102 5-9. MIRR and DFCT Signal Generation ................................................................................................ 103 5-10. DFCT Countermeasure Circuit ........................................................................................................ 104 5-11. Anti-Shock Circuit ............................................................................................................................ 104 5-12. Brake Circuit .................................................................................................................................... 105 5-13. COUT Signal ................................................................................................................................... 106 5-14. Serial Readout Circuit ...................................................................................................................... 106 5-15. Writing to the Coefficient RAM ........................................................................................................ 107 5-16. PWM Output .................................................................................................................................... 107 5-17. DIRC Input Pin ................................................................................................................................. 109 5-18. Servo Status Changes Produced by the LOCK Signal ................................................................... 110 5-19. Description of Commands and Data Sets ....................................................................................... 110 5-20. List of Servo Filter Coefficients ........................................................................................................ 125 5-21. Filter Composition ............................................................................................................................ 127 5-22. TRACKING and FOCUS Frequency Response .............................................................................. 134 [6] Application Circuit .................................................................................................................................. 135 Explanation of abbreviations AVRG: AGCNTL: FCS: TRK: SLD: DFCT: Average Auto gain control Focus Tracking Sled Defect - 15 - CXD3003R [1] CPU Interface 1-1. CPU Interface Timing * CPU interface This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below. 30ns or more CLOK DATA D0 D1 D18 D19 D20 D21 D22 D23 750ns or more XLAT Registers Valid * The internal registers are initialized by a reset when XRST = 0. 1-2. CPU Interface Command Table Total bit length for each register Register 0 to 2 3 4 to 6 7 8 9 A B C D E Total bit length 8 bits 8 to 24 bits 16 bits 20 bits 24 bits 20 bits 28 bits 20 bits 16 bits 20 bits 20 bits - 16 - Command Table ($0X to 1X) Data 2 D16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FOCUS SEARCH VOLTAGE DOWN -- FOCUS SEACH VOLTAGE UP -- -- -- ANTI SHOCK ON ANTI SHOCK OFF -- -- BRAKE ON -- BRAKE OFF -- TRACKING GAIN NORMAL -- TRACKING GAIN UP -- TRACKING GAIN UP FILTER SELECT 1 -- TRACKING GAIN UP FILTER SELECT 2 -- --: Don't care CXD3003R D15 D14 D13 D12 D11 D10 D9 D8 D7 D3 D2 D1 D0 D6 D5 D4 Data 3 Data 4 Data 5 Address Data 1 Register Command D23 to D20 D19 D18 D17 1 0 -- 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FOCUS CONTROL 0000 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 -- 1 0 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- 1 0 -- -- -- -- -- -- -- -- -- -- -- 1 0 -- 1 - 17 - 1 0 -- 0 -- -- -- 1 -- -- 0 -- 1 TRACKING CONTROL 0001 -- -- 0 -- -- 1 -- -- -- -- -- -- Command Table ($2X to 3X) Data 2 D16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 5 D4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- D3 -- -- -- -- D2 -- -- -- -- D1 -- -- -- -- D0 -- -- -- -- SLED KICK LEVEL (1 x basic value) (Default) -- SLED KICK LEVEL (2 x basic value) -- SLED KICK LEVEL (3 x basic value) -- -- -- SLED KICK LEVEL (4 x basic value) -- --: Don't care -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 4 D8 -- -- -- D7 D6 D5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 3 D12 -- -- -- -- -- -- -- -- -- -- -- -- -- D11 D10 D9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 2 D15 -- -- -- -- -- -- -- -- -- -- -- -- D14 D13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 1 0 1 TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE D15 D14 D13 D12 D11 D10 D9 D8 D7 D3 D2 D1 D0 D6 D5 D4 Data 3 Data 4 Data 5 Address Data 1 Register Command D23 to D20 D19 D18 D17 0 0 -- 0 1 -- 1 0 -- 1 1 -- 2 TRACKING MODE 0010 -- -- 0 -- -- 0 -- -- 1 - 18 - Data 1 D16 0 1 0 1 -- -- 1 Address Register Command D23 to D20 D19 D18 D17 0 0 0 0 0 0 3 SELECT 0011 0 0 1 0 0 1 CXD3003R Command Table ($340X) Address 4 D10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K03) SLED LOW BOOST FILTER B-H KRAM DATA (K04) SLED LOW BOOST FILTER B-L KRAM DATA (K05) SLED OUTPUT GAIN KRAM DATA (K06) FOCUS INPUT GAIN KRAM DATA (K07) SLED AUTO GAIN KRAM DATA (K08) FOCUS HIGH CUT FILTER A KRAM DATA (K09) FOCUS HIGH CUT FILTER B KRAM DATA (K0A) FOCUS LOW BOOST FILTER A-H KRAM DATA (K0B) FOCUS LOW BOOST FILTER A-L KRAM DATA (K0C) FOCUS LOW BOOST FILTER B-H KRAM DATA (K0D) FOCUS LOW BOOST FILTER B-L KRAM DATA (K0E) FOCUS PHASE COMPENSATE FILTER A KRAM DATA (K0F) FOCUS DEFECT HOLD GAIN CXD3003R 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K02) SLED LOW BOOST FILTER A-L 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K01) SLED LOW BOOST FILTER A-H 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K00) SLED INPUT GAIN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data 1 Data 2 Address 1 Address 2 Address 3 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - 19 - 3 SELECT 0011 0100 0000 Command Table ($341X) Address 4 D10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K13) FOCUS AUTO GAIN KRAM DATA (K14) HPTZC / AUTO GAIN HIGH PASS FILTER A KRAM DATA (K15) HPTZC / AUTO GAIN HIGH PASS FILTER B KRAM DATA (K16) ANTI SHOCK HIGH PASS FILTER A KRAM DATA (K17) HPTZC / AUTO GAIN LOW PASS FILTER B KRAM DATA (K18) FIX KRAM DATA (K19) TRACKING INPUT GAIN KRAM DATA (K1A) TRACKING HIGH CUT FILTER A KRAM DATA (K1B) TRACKING HIGH CUT FILTER B KRAM DATA (K1C) TRACKING LOW BOOST FILTER A-H KRAM DATA (K1D) TRACKING LOW BOOST FILTER A-L KRAM DATA (K1E) TRACKING LOW BOOST FILTER B-H KRAM DATA (K1F) TRACKING LOW BOOST FILTER B-L 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K12) ANTI SHOCK INPUT GAIN 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K11) FOCUS OUTPUT GAIN 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K10) FOCUS PHASE COMPENSATE FILTER B D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data 1 Data 2 Address 1 Address 2 Address 3 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - 20 - 3 SELECT 0011 0100 0001 CXD3003R Command Table ($342X) Address 4 D10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K23) TRACKING AUTO GAIN KRAM DATA (K24) FOCUS GAIN DOWN HIGH CUT FILTER A KRAM DATA (K25) FOCUS GAIN DOWN HIGH CUT FILTER B KRAM DATA (K26) FOCUS GAIN DOWN LOW BOOST FILTER A-H KRAM DATA (K27) FOCUS GAIN DOWN LOW BOOST FILTER A-L KRAM DATA (K28) FOCUS GAIN DOWN LOW BOOST FILTER B-H KRAM DATA (K29) FOCUS GAIN DOWN LOW BOOST FILTER B-L KRAM DATA (K2A) FOCUS GAIN DOWN PHASE COMPENSATE FILTER A KRAM DATA (K2B) FOCUS GAIN DOWN DEFECT HOLD GAIN KRAM DATA (K2C) FOCUS GAIN DOWN PHASE COMPENSATE FILTER B KRAM DATA (K2D) FOCUS GAIN DOWN OUTPUT GAIN KRAM DATA (K2E) NOT USED KRAM DATA (K2F) NOT USED CXD3003R 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K22) TRACKING OUTPUT GAIN 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K21) TRACKING PHASE COMPENSATE FILTER B 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K20) TRACKING PHASE COMPENSATE FILTER A D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data 1 Data 2 Address 1 Address 2 Address 3 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - 21 - 3 SELECT 0011 0100 0010 Command Table ($343X) Address 4 D10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K32) NOT USED KRAM DATA (K33) ANTI SHOCK HIGH PASS FILTER B-H KRAM DATA (K34) ANTI SHOCK HIGH PASS FILTER B-L KRAM DATA (K35) ANTI SHOCK FILTER COMPARATE GAIN KRAM DATA (K36) TRACKING GAIN UP2 HIGH CUT FILTER A KRAM DATA (K37) TRACKING GAIN UP2 HIGH CUT FILTER B KRAM DATA (K38) TRACKING GAIN UP2 LOW BOOST FILTER A-H KRAM DATA (K39) TRACKING GAIN UP2 LOW BOOST FILTER A-L KRAM DATA (K3A) TRACKING GAIN UP2 LOW BOOST FILTER B-H KRAM DATA (K3B) TRACKING GAIN UP2 LOW BOOST FILTER B-L KRAM DATA (K3C) TRACKING GAIN UP PHASE COMPENSATE FILTER A KRAM DATA (K3D) TRACKING GAIN UP PHASE COMPENSATE FILTER B KRAM DATA (K3E) TRACKING GAIN UP OUTPUT GAIN KRAM DATA (K3F) NOT USED CXD3003R 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K31) ANTI SHOCK LOW PASS FILTER B 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K30) FIX D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data 1 Data 2 Address 1 Address 2 Address 3 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - 22 - 3 SELECT 0011 0100 0011 Command Table ($344X) Address 4 D10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K43) TRACKING HOLD FILTER B-H KRAM DATA (K44) TRACKING HOLD FILTER B-L KRAM DATA (K45) TRACKING HOLD FILTER OUTPUT GAIN KRAM DATA (K46) NOT USED KRAM DATA (K47) NOT USED KRAM DATA (K48) FOCUS HOLD FILTER INPUT GAIN KRAM DATA (K49) FOCUS HOLD FILTER A-H KRAM DATA (K4A) FOCUS HOLD FILTER A-L KRAM DATA (K4B) FOCUS HOLD FILTER B-H KRAM DATA (K4C) FOCUS HOLD FILTER B-L KRAM DATA (K4D) FOCUS HOLD FILTER OUTPUT GAIN KRAM DATA (K4E) NOT USED KRAM DATA (K4F) NOT USED CXD3003R 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K42) TRACKING HOLD FILTER A-L 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K41) TRACKING HOLD FILTER A-H 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K40) TRACKING HOLD FILTER INPUT GAIN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data 1 Data 2 Address 1 Address 2 Address 3 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - 23 - 3 SELECT 0011 0100 0100 Command Table ($34FX to 3FX) Address 2 D16 0 1 -- FOCUS BIAS LIMIT FOCUS BIAS DATA TRVSC DATA -- 1 FB7 FB3 TV3 Data 4 D4 D3 D2 D1 D0 FOCUS SEARCH SPEED/ VOLTAGE/AUTO GAIN DTZC/TRACK JUMP VOLTAGE/AUTO GAIN FZSL/SLED MOVE/ Voltage/AUTO GAIN LEVEL/AUTO GAIN/ DFSW/ (Initialize) 0 0 0 0 0 0 0 SERIAL DATA READ MODE/SELECT SJHD INBK MTI0 FOCUS BIAS 0 BTS1 BTS0 MRC1 MRC0 0 0 0 0 0 DRR2 DRR1 DRR0 0 0 0 0 0 0 0 0 0 0 0 0 0 Operation for MIRR/ DFCT/FOK TZC/COUT BOTTOM/MIRR SLED FILTER LKIN COIN MDFI MIRI XT1D Filter ASFG FTQ LPAS SRO1 SRO0 AGHF 0 Others --: Don't care TV2 TV1 TV0 FB2 FB1 TV7 Data 3 D8 D7 D6 D5 TV6 TV5 TV4 FB6 FB5 FB4 1 Data 2 D12 FS3 FS2 FS1 FS0 TJ2 TJ1 TJ3 D11 D10 D9 0 0 TV9 TV8 0 1 FB9 FB8 FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 0 0 Data 1 D16 1 0 1 0 1 0 1 0 1 0 1 0 AGG4 XT4D XT2D SFID SFSK THID THSK 0 COSS COTS CETZ CETF COT2 COT1 MOT2 0 FBON FBSS FBUP FBV1 FBV0 0 DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0 0 0 TDZC DTZC TJ5 TJ4 FT1 FT0 FS5 FS4 D15 D14 D13 1 1 1 1 1 1 1 1 0 1 1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D3 D2 D1 D0 D6 D5 D4 Data 1 Data 2 Data 3 Address 1 Register Command D23 to D20 D19 D18 D17 0 1 0 0011 0 1 0 0 1 0 Address D23 to D20 D19 D18 D17 0 1 0 FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0 0 1 1 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0 0 1 1 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 - 24 - TJD0 FPS1 FPS0 TPS1 TPS0 TLD2 TLD1 TLD0 F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD 3 SELECT 1 0 0 1 0 0 0011 1 0 1 1 0 1 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT 1 1 0 1 1 0 1 1 1 1 1 1 CXD3003R Command Table ($4X to EX) Data 1 D24 0 MT0 0 -- -- -- LSSL 0 0 AS3 AS2 AS1 MT2 MT1 -- AS0 MT3 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 Data 2 Data 3 Data 4 Address Register Command D27 D26 D25 4 Auto sequence 0 1 0 5 1 0 0 -- -- -- 0 0 0 TR3 TR2 TR1 0 0 TR0 0 Blind (A, E), Brake (B), Overflow (C, G) 0 1 0 -- 6 0 KF0 0 -- -- 0 0 0 SD3 SD2 SD1 KF2 KF1 SD0 KF3 Sled KICK, BRAKE (D), KICK (F) 0 1 1 -- -- 7 1 256 32 128 64 16 32768 16384 8192 1024 512 4096 2048 Auto sequence (N) track jump count setting 0 1 1 8 4 2 1 8 0 KSL3 KSL1 0 DAC ATT KSL2 1 0 1 256 0 1 PWM MD MODE specification 1 ASHS SOCT DCLV DSPB ASEQ DPLL BiliGL BiliGL DAC FLFC XWOC ON/OFF ON/OFF ON/OFF ON/OFF MAIN SUB EMP 0 Mute 8192 1024 512 4096 2048 128 0 VP3 SFSL VC2C 32768 16384 Gain Gain Gain Gain Gain Gain PCC1 PCC0 MDP1 MDP0 MDS1 MDS0 DCLV1 DCLV0 DCLV TB TP VP6 CM1 VP7 CM2 VP5 CLVS Gain CM0 EPWM SPDC ICAP VP4 0 ATT 0 0 CD- DOUT DOUT WSEL ROM Mute Mute-F VCO SEL2 VCO SEL KSL0 0 VC01 VCO1 XVCO2 VCO2 CS1 CS0 THRU CS PLM3 PLM2 PLM1 PLM0 9 Function specification 1 0 0 - 25 - 64 0 VP2 0 CM3 Data 5 Data 2 Data 3 Data 4 D7 ERC4 D6 D5 SCOR SCSY SEL D4 0 A Audio CTRL 1 0 1 PCT1 PCT2 DADS SOC2 AT1D7 AT1D6 AT1D5 AT1D4 AT1D3 AT1D2 AT1D1 AT1D0 32 0 VP1 16 0 VP0 HIFC LPWR VPON 8 -- VP CTL1 4 -- VP CTL0 2 -- 0 1 -- 0 INV Gain Gain FCSW VPCO CAV1 CAV0 --: Don't care Data 6 D3 -- D2 -- D1 -- D0 -- CXD3003R AT2D7 AT2D6 AT2D5 AT2D4 AT2D3 AT2D2 AT2D1 AT2D0 B Traverse monitor counter setting 1 0 1 C Spindle servo coefficient setting 1 1 0 D CLV CTRL 1 1 0 E SPD mode 1 1 1 Register Command Address Data 1 8 MODE specification 1 0 0 0 A Audio CTRL 1 0 1 0 1-3. CPU Command Presets Command Preset Table ($0X to 34X) Data 2 D16 0 -- -- -- -- -- -- Data 5 D4 D3 -- -- D2 -- D0 -- Data 2 D4 D3 D2 D0 D0 KRAM DATA ($3400XX to $344fXX) --: Don't care D0 -- SLED KICK LEVEL (1 x basic value) (Default) -- -- -- -- -- -- -- -- -- -- -- Data 4 D8 -- -- Data 1 D8 D7 D6 D5 -- -- D7 D6 D5 -- -- -- -- -- -- -- -- Data 3 D12 -- Address 3 D12 D11 D10 D9 -- -- -- D11 D10 D9 -- -- -- -- -- -- -- -- -- -- -- Data 2 D15 -- Address 2 D16 0 0 D15 D14 D13 -- -- D14 D13 -- -- -- -- -- -- -- -- -- 1 0 -- -- -- D15 D14 D13 D12 D11 D10 D9 D8 D7 D3 D2 D1 D0 FOCUS SERVO OFF, 0V OUT TRACKING GAIN UP FILTER SELECT 1 TRACKING SERVO OFF SLED SERVO OFF D6 D5 D4 Data 3 Data 4 Data 5 Address Data 1 Register Command D23 to D20 D19 D18 D17 0 FOCUS CONTROL 0000 0 0 0 1 TRACKING CONTROL 0001 0 0 0 2 TRACKING MODE 0010 0 0 0 Address D16 0 Data 1 Register Command D23 to D20 D19 D18 D17 0011 0 0 0 Address 1 3 SELECT - 26 - See "Coefficient ROM Preset Values Table". D23 to D20 D19 D18 D17 0011 0 1 0 CXD3003R Command Preset Table ($34FX to 3FX) Address 2 D16 0 1 0 0 0 FOCUS BIAS LIMIT FOCUS BIAS DATA TRVSC DATA 0 0 0 0 Data 4 D4 D3 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 D2 D1 D0 FOCUS SEARCH SPEED/ VOLTAGE AUTO GAIN DTZC/TRACK JUMP VOLTAGE AUTO GAIN FZSL/SLED MOVE/ Voltage/AUTO GAIN LEVEL/AUTO GAIN/ DFSW/ (Initialize) 0 SERIAL DATA READ MODE/SELECT 0 FOCUS BIAS Operation for MIRR/ DFCT/FOK 0 TZC/COUT BOTTOM/MIRR SLED FILTER Filter Others --: Don't care CXD3003R 0 0 1 0 0 0 0 0 0 0 0 Data 3 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 D7 D6 D5 0 0 0 0 0 0 0 0 0 1 1 Data 2 D12 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 D11 D10 D9 0 0 0 0 0 1 0 0 0 0 0 0 Data 1 D16 1 0 1 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 D15 D14 D13 1 1 1 1 1 1 1 1 0 1 1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D3 D2 D1 D0 D6 D5 D4 Data 1 Data 2 Data 3 Address 1 Register Command D23 to D20 D19 D18 D17 0 1 0 0011 0 1 0 0 1 0 Address D23 to D20 D19 D18 D17 0 1 0 0 1 1 0 1 1 - 27 - 3 SELECT 1 0 0 1 0 0 0011 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 Command Preset Table ($4X to EX) Data 1 D24 0 0 0 0 -- -- -- -- 0 0 0 0 0 0 0 0 0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 Data 2 Data 3 Data 4 Address Register Command D27 D26 D25 4 Auto sequence 0 1 0 5 Blind (A, E), Brake (B), Overflow (C, G) 0 1 0 1 0 -- -- -- 0 0 0 0 0 1 0 0 0 1 0 -- 6 Sled KICK, BRAKE (D), KICK (F) 0 0 0 1 0 -- -- 0 0 0 0 0 1 1 0 0 1 1 -- -- 7 Auto sequence (N) track jump count setting 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 8 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 MODE specification 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 -- 0 0 0 0 1 0 -- 0 0 0 0 1 0 -- 0 0 0 1 1 0 -- 0 0 --: Don't care 9 Function specification 1 0 0 - 28 - Data 5 Data 2 Data 3 Data 4 D7 0 1 D6 0 1 D5 0 1 D4 0 1 A Audio CTRL 1 0 1 B Traverse monitor counter setting 1 0 1 C Spindle servo coefficient setting 1 1 0 D CLV CTRL 1 1 0 E SPD mode 1 1 1 Data 6 D3 -- 1 D2 -- 1 D1 -- 1 D0 -- 1 Register Command Address Data 1 8 MODE specification 1 0 0 0 CXD3003R A Audio CTRL 1 0 1 0 CXD3003R - 29 - CXD3003R - 30 - CXD3003R 1-4. Description of SENS Signals SENS output Microcomputer serial register (latching not required) $0X $1X $2X $38 $38 $30 to 37 $3A $3B to 3F $3904 $3908 $390C $391C $391D $391F $4X $5X $6X $AX $BX $CX $EX $7X, 8X, 9X, DX, FX ASEQ = 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z GFS COMP COUT OV64 Z ASEQ = 1 FZC AS TZC AGOK XAVEBSY SSTP FBIAS Count STOP SSTP TE Avrg Reg. FE Avrg Reg. VC Avrg Reg. TRVSC Reg. FB Reg. RFDC Avrg Reg. XBUSY FOK Servo SENS GFS COMP COUT OV64 0 Output data length -- -- -- -- -- -- -- -- 9 bit 9 bit 9 bit 9 bit 9 bit 8 bit -- -- -- -- -- -- -- -- $38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement. SSTP is output in all other cases. - 31 - CXD3003R Description of SENS Signals SENS output Z XBUSY FOK GFS COMP The SENS pin is high impedance. Low while the auto sequencer is in operation, high when operation terminates. Outputs the same signal as the FOK pin. High for "focus OK". High when the regenerated frame sync is obtained with the correct timing. Counts the number of tracks set with Reg.B. High when Reg.B is latched, low when the initial Reg.B number is input by CNIN. Counts the number of tracks set with Reg.B. High when Reg.B is latched, toggles each time the Reg.B number is input by CNIN. While $44 and $45 are being executed, toggles with each CNIN 8-count instead of the Reg.B number. Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing through the sync detection filter. COUT OV64 - 32 - CXD3003R The meaning of the data for each address is explained below. $4X commands Register name 4 AS3 Data 1 Command AS2 AS1 AS0 MT3 Data 2 MAX timer value MT2 MT1 MT0 LSSL Data 3 Timer range 0 0 0 Command Cancel Fine Search Focus-on 1-Track Jump 10-Track Jump 2N-Track Jump M Track Move AS3 0 0 0 1 1 1 1 AS2 0 1 1 0 0 1 1 AS1 0 0 1 0 1 0 1 AS0 0 RXF 1 RXF RXF RXF RXF RXF = 0 Forward RXF = 1 Reverse * When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted. * When the Track jump commands ($44 to $45, $48 to $4D) are canceled, $25 is sent and the auto sequence is interrupted. MAX timer value MT3 23.2ms 1.49s MT2 11.6ms 0.74s MT1 5.8ms 0.37s MT0 2.9ms 0.18s LSSL 0 1 0 0 0 Timer range 0 0 0 0 0 0 * To disable the MAX timer, set the MAX timer value to 0. $5X commands Timer Blind (A, E), Overflow (C, G) Brake (B) TR3 0.18ms 0.36ms TR2 0.09ms 0.18ms TR1 0.045ms 0.09ms TR0 0.022ms 0.045ms - 33 - CXD3003R $6X commands Register name 6 SD3 Timer When executing KICK (D) $44 or $45 When executing KICK (D) $4C or $4D Timer KICK (F) Data 1 KICK (D) SD2 SD1 SD0 KF3 SD3 23.2ms 11.6ms KF3 0.72ms Data 2 KICK (F) KF2 KF1 SD2 11.6ms 5.8ms KF2 0.36ms KF0 SD1 5.8ms 2.9ms KF1 0.18ms SD0 2.9ms 1.45ms KF0 0.09ms $7X commands Auto sequence track jump count setting Command Data 1 Data 2 Data 3 Data 4 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 29 28 27 26 25 24 23 22 21 20 Auto sequence track jump 215 214 213 212 211 210 count setting This command is used to set N when a 2N-track jump is executed, to set M when an M-track move is executed and to set the jump count when fine search is executed for auto sequence. * The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count depends on the mechanical limitations of the optical system. * When the track jump count is from 0 to 15, the COUT signal counted for 2N-track jumps and M-track moves; when the count is 16 or over, the MIRR signal is counted. For fine search, the COUT signal is counted. - 34 - CXD3003R $8X commands Command MODE specification Data 1 D23 D22 D21 D20 D19 Data 2 D18 D17 D16 CD- DOUT DOUT VCO VCO ASHS SOCT WSEL SEL1 SEL2 ROM Mute Mute-F Command bit CDROM = 1 CDROM = 0 C2PO timing 1-3 1-3 Processing CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed. Command bit DOUT Mute = 1 DOUT Mute = 0 Processing When Digital Out is on (MD2 pin = 1), DOUT output is muted. When Digital Out is on, DOUT output is not muted. Command bit D. out Mute F = 1 D. out Mute F = 0 Processing When Digital Out is on (MD2 pin = 1), DA output is muted. DA output mute is not affected when Digital Out is either on or off. MD2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Other mute conditions 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DOUT Mute D.out Mute F DOUT output 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 - dB 0dB OFF DA output for 48-bit slot DA output for 64-bit slot 0dB 0dB - dB - dB 0dB - dB 0dB 0dB - dB - dB See mute conditions (1), (2), and (4) to (6) under $AX commands for other mute conditions. - 35 - CXD3003R Command bit WSEL = 1 WSEL = 0 Sync protection window width 26 channel clock 6 channel clock Application Anti-rolling is enhanced. Sync window protection is enhanced. In normal-speed playback, channel clock = 4.3218MHz. Command bit ASHS = 0 ASHS = 1 Function The command transfer rate to SSP is set to normal speed. The command transfer rate to SSP is set to half speed. See "4-8. Playback Speed" for settings. Command bit SOCT = 0 SOCT = 1 Sub Q is output from the SQSO pin. Function Each output signal is output from the SQSO pin. Input the readout clock to SQCK. (See Timing Chart 2-4.) - 36 - CXD3003R Command MODE specification Data 2 D19 D18 D17 D16 D15 KSL3 Data 3 D14 KSL2 D13 KSL1 D12 KSL0 VCO VCO ASHS SOCT SEL1 SEL2 See the previous page. Command bit VCOSEL1 = 0 VCOSEL1 = 1 Processing Multiplier PLL VCO1 is set to normal speed. Multiplier PLL VCO1 is set to approximately twice the normal speed. This setting is valid only when the low-speed VCO is selected by VCO1 CS1 and CS0. Command bit KSL3 0 0 1 1 KSL2 0 1 0 1 Processing Output of multiplier PLL VCO1 selected by VCO1 CS1 and CS0 is 1/1 frequency-divided. Output of multiplier PLL VCO1 selected by VCO1 CS1 and CS0 is 1/2 frequency-divided. Output of multiplier PLL VCO1 selected by VCO1 CS1 and CS0 is 1/4 frequency-divided. Output of multiplier PLL VCO1 selected by VCO1 CS1 and CS0 is 1/8 frequency-divided. Command bit VCOSEL2 = 0 VCOSEL2 = 1 Processing Wide-band PLL VCO2 is set to normal speed. Wide-band PLL VCO2 is set to approximately twice the normal speed. This setting is valid only when the low-speed VCO is selected by VCO2 CS. Command bit KSL1 0 0 1 1 KSL0 0 1 0 1 Processing Output of wide-band PLL VCO2 selected by VCO2 CS is 1/1 frequency-divided. Output of wide-band PLL VCO2 selected by VCO2 CS is 1/2 frequency-divided. Output of wide-band PLL VCO2 selected by VCO2 CS is 1/4 frequency-divided. Output of wide-band PLL VCO2 selected by VCO2 CS is 1/8 frequency-divided. - 37 - CXD3003R Command MODE specification Data 4 D11 VCO1 CS1 D10 VCO1 CS0 D9 XVCO2 THRU D8 VCO2 CS Command bit VCO1CS1 VCO1CS0 0 0 1 1 0 1 0 1 Processing No.1 (Low-speed VCO for CXD3003) No.2 (Middle-speed VCO for CXD3003) No.3 (High-speed VCO for CXD3003) No.4 The CXD3003R has four multiplier PLL VCO1s, and this command selects one of these VCO1s. Four VCOs are No.3, No.4, No.2 and No.1 in order of the maximum frequency. Command bit XVCO2 THRU = 0 XVCO2 THRU = 1 Processing V16M output is connected internally to VCKI. V16M output is not connected internally. Input the clock from VCKI. This command sets internal or external connection for the VCO2 used in CAV-W mode. Command bit VCO2 CS = 0 VCO2 CS = 1 Processing Low-speed wide-band PLL VCO2 is selected. High-speed wide-band PLL VCO2 is selected. The CXD3003R has two wide-band PLL VCO2, and this command selects one of these VCO1. Block diagram for VCO1 and VCO2 including VCOSEL1, VCOSEL2, KSL0 to 3, VCO1CS0, VCO1CS1 and VCO2 CS. - 38 - CXD3003R Block Diagram of VCO Internal Path VCO1SEL No. 1 VCO1 1/1 No. 2 VCO1 Selector Selector 1/2 To DSP interior No. 3 VCO1 VCO1CS1, 0 No. 4 VCO1 1/4 1/8 KSL3, 2 VCO1 internal path VCO2SEL Low-speed VCO2 1/1 Selector Selector 1/2 To DSP interior 1/4 High-speed VCO2 VCO2CS 1/8 KSL1, 0 VCO2 internal path - 39 - CXD3003R Command MODE specification Data 5 D7 ERC4 D6 SCOR SEL D5 SCSY D4 0 Command bit ERC4 = 0 ERC4 = 1 Processing C2 error double correction is performed when DSPB = 1. C2 error quadruple correction is performed when DSPB = 1. Command bit SCOR SEL = 0 SCOR SEL = 1 FSW signal is output. Processing GRSCOR (protected SCOR) is output. Used when outputting GRSCOR from the FSW pin. Command bit SCSY = 0 SCSY = 1 No processing. Processing GRSCOR (protected SCOR) synchronization is applied again. Used to resynchronize GRSCOR. the rising edge signal of this command bit is used internally. Therefore, when resynchronizing GRSCOR, first return the setting to 0 and then set to 1. GRSCOR achieves the crystal accuracy by removing the jitter components included in the SCOR signal. This signal is synchronized with PCMDATA. The resynchronization conditions are when GTOP = high or when the SCSY pin = high. (Same as when SCSY = 1 is sent by the $8X command.) - 40 - CXD3003R $9X commands Command Function specification Data 1 D23 D22 D21 D20 D19 BiliGL MAIN Data 2 D18 BiliGL SUB D17 FLFC D16 XWOC DCLV DSPB A.SEQ D.PLL ON-OFF ON-OFF ON-OFF ON-OFF Command bit CLV mode In CLVS mode Contents FSW = low, MON = high, MDS = Z; MDP = servo control signal, carrier frequency of 230Hz at TB = 0 and 460Hz at TB = 1. FSW = Z, MON = high; MDS = speed control signal, carrier frequency of 7.35kHz; MDP = phase control signal, carrier frequency of 1.8kHz. When DCLV PWM MDS = PWM polarity signal, carrier frequency and MD = 1 of 132kHz (Prohibited in CLV-W MDP = PWM absolute value output (binary), and CAV-W modes) carrier frequency of 132kHz When DCLV PWM and MD = 0 MDS = Z MDP = ternary PWM output, carrier frequency of 132kHz DCLV on/off = 0 In CLVP mode DCLV on/off = 1 (FSW, MON not required) In CLVS and CLVP modes When DCLV on/off = 1 for the Digital CLV servo, the sampling frequency of the internal digital filter switches simultaneously with the CLVP/CLVS switching. Therefore, the cut-off frequency for the CLVS is fc = 70Hz when TB = 0, and fc = 140Hz when TB = 1. Command bit DSPB = 0 DSPB = 1 Processing Normal-speed playback, C2 error quadruple correction. Double-speed playback, C2 error double correction. (quadruple correction when ERC4 = 1) FLFC is normally 0. FLFC is 1 in CAV-W mode, for any playback speed. Command bit DPLL = 0 Meaning RFPLL is analog. PDO, VCOI and VCOO are used. DPLL = 1 RFPLL is digital. PDO is high impedance. External parts for the FILI, FILO and PCO pins are required even when analog PLL is selected. Command bit BiliGL SUB = 0 BiliGL SUB = 1 BiliGL MAIN = 0 STEREO SUB BiliGL MAIN = 1 MAIN Mute Definition of bilingual capable MAIN, SUB and STEREO The left channel input is output to the left and right channels for MAIN. The right channel input is output to the left and right channels for SUB. The left and right channel inputs are output to the left and right channels for STEREO. - 41 - CXD3003R Command bit XWOC 0 0 1 1 External pin XWO L H L H DAC sync window is open. Processing DAC sync window is not open. This is used to perform resynchronization to DAC. This command has the function equal to the external pin XWO's. Set to high or 1 for the external pin or unused side of the command register. * I/O sync circuit Related pins: LRCK and XWO, Related command: XWOC During normal operation, the I/O sync circuit automatically synchronizes with the input LRCK, and its operation proceeds in phase with the serial input data. However, there is a chance that synchronization will not be performed if there is a great deal of jitter in LRCK, or if the power has just been turned on, etc. In this case, forced synchronization is possible by setting the XWO pin or command XWOC low (0) for 2/Fs or more. Forced synchronization must also be performed when switching the clock system such as when switching from CLV mode to CAV mode and vice versa, or when switching the operating frequency, etc. The forced synchronization operation is performed at the second rising edge of LRCK after the XWO pin is set low or the XWOC command 19 set to 0. Data 3 D15 DAC EMPH D14 DAC ATT D13 0 D12 0 Command Function specification These command bits control the DAC. Command bit DAC EMPH = 1 DAC EMPH = 0 Processing Applies digital de-emphasis. The emphasis constants are 1 = 50s and 2 = 15s when Fs = 44.1kHz. Turns digital de-emphasis off. Command bit DAC ATT = 1 DAC ATT = 0 Processing Identical digital attenuation control is used for both channels 1 and 2. When common attenuation data is specified, the attenuation values for channel 1 are used. Independent digital attenuation control is used for both channels 1 and 2. Note) For normal stereo, channel 1 is the left channel and channel 2 is the right channel. - 42 - CXD3003R Command Function specification Data 4 D11 PLM3 D10 PLM2 D9 PLM1 D8 PLM0 * DAC PLAY MODE By controlling these command bits, the DAC outputs channel 1 and channel 2 can be output in 16 different combinations of left channel, right channel, left + right channel, and mute. The relationship between the commands and the outputs is shown in the table on the following page. PLM3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PLM2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PLM1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PLM0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Channel 1 output Mute L R L+R Mute L R L+R Mute L R L+R Mute L R L+R Channel 2 output Remarks Mute Mute Mute Mute L L L L R R R R L+R L+R L+R L+R Mono Stereo Reverse Mute Note) For normal stereo, channel 1 is the left channel and channel 2 is the right channel. The output data of L + R is (L + R)/2 to prevent overflow. - 43 - CXD3003R $AX commands Command Audio CTRL Data 1 D23 0 D22 0 D21 Mute D20 ATT D19 PCT1 Data 2 D18 PCT2 D17 DADS D16 SOC2 Command bit Mute = 0 Mute = 1 Meaning Mute off if other mute conditions are not set. Mute on. Peak register reset. Command bit ATT = 0 ATT = 1 Meaning Attenuation off -12dB Mute conditions (1) When register A mute = 1. (2) When Mute pin = 1. (3) When register 8 D.out Mute F = 1 and the Digital Out is on (MD2 pin = 1). (4) When GFS stays low for over 35ms (during normal speed). (5) When register 9 BiliGL MAIN = Sub = 1. (6) When register A PCT1 = 1 and PCT2 = 0. (1) to (4) perform zero-cross muting with a 1ms time limit. Command bit PCT1 0 0 1 1 PCT2 0 1 0 1 Meaning Normal mode Level meter mode Peak meter mode Normal mode PCM Gain x 0dB x 0dB Mute x 0dB ECC error correction ability C1: double; C2: quadruple C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double Description of level meter mode (see Timing Chart 1-4.) * When the LSI is set to this mode, it performs digital level meter functions. * When the 96-bit clock is input to SQCK, 96 bits of data are output to SQSO. The initial 80 bits are Sub Q data (see 2. Subcode Interface). The last 16 bits are LSB first, which are 15-bit PCM data (absolute values) and an L/R flag. The L/R flag is high when the 15-bit PCM data is from the left channel and low when the data is from the right channel. * The PCM data is reset and the L/R flag is reversed after one readout. Then maximum value measuring continues until the next readout. - 44 - CXD3003R Description of peak meter mode (see Timing Chart 1-5.) * When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from the left or right channel. The 96-bit clock must be input to SQCK to read out this data. * When the 96-bit clock is input, 96 bits of data are output to SQSO and the value is set in the LSI internal register again. In other words, the PCM maximum value detection register is not reset by the readout. * To reset the PCM maximum value register to zero, set PCT1 = PCT2 = 0 or set the $AX mute. * The Sub Q absolute time is automatically controlled in this mode. In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in the memory. Normal operation is conducted for the relative time. * The final bit (L/R flag) of the 96-bit data is normally 0. * The pre-value hold and average value interpolation data are fixed to level (- ) in this mode. Command bit DADS = 0 DADS = 1 Processing Set to 0 when crystal = 33.8688MHz. Set to 1 when crystal = 16.9344MHz. Command bit SOC2 = 0 SOC2 = 1 Processing The SENS signal is output from the SENS pin as usual. The SQSO pin signal is output from the SENS pin. SENS output switching * This command enables the SQSO pin signal to be output from the SENS pin. When SOC2 = 0, SENS output is performed as usual. When SOC2 = 1, the SQSO pin signal is output from the SENS pin. At this time, the readout clock is input to the SCLK pin. Note) SOC2 should be switched when SQCK = SCLK = high. - 45 - CXD3003R * DAC digital attenuator Command Audio Ctrl Data 3 D15 D14 D13 D12 D11 Data 4 D10 D9 D8 D7 Data 5 D6 D5 D4 D3 Data 6 D2 D1 D0 AT1D AT1D AT1D AT1D AT1D AT1D AT1D AT1D AT2D AT2D AT2D AT2D AT2D AT2D AT2D AT2D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Note) AT1D7 to AT1D0 are the channel 1 ATT control bits. AT2D7 to AT2D0 are the channel 2 ATT control bits. Command bits AT1D7 to AT1D0 (AT2D7 to AT2D0) FF (H) FE (H) 01 (H) 00 (H) Audio output 0dB -0.034dB -48.131dB - The attenuation data consists of 8 bits each for channels 1 and 2; the DAC ATT bit can be used to control channels 1 and 2 with common attenuation data. (When common attenuation data is specified, the attenuation values for channel 1 are used.) An attenuation value, from 00 (H) to FF (H), is determined according to the following equation: ATT = 20 log [input data/255] dB Example: When the attenuation data is FA (H): ATT = 20 log [250/255] dB = -0.172dB * Soft mute With the soft mute function, when the attenuation data goes from FF (H) and 00 (H) and vice versa, muting is turned on and off over the muting time of 1024Fs [s] = 23.2 [ms] (Fs = 44.1kHz). * Attenuation Assume the attenuation data ATT1, ATT2 and ATT3, where ATT1 > ATT3 > ATT2. First, assume ATT1 is transferred and then ATT2 is transferred. If ATT2 is transferred before ATT1 is reached (state "A" in the diagram), then the value continues approaching ATT2. Next, if ATT3 is transferred before ATT2 is reached (state "B" or "C" in the diagram), the attenuation begins approaching ATT3 from the current point. Note that it takes 1024/Fs [s] (Fs = 44.1kHz for CD players) to transit between attenuation data (from 0dB to - ). 0dB A ATT1 B ATT3 C ATT2 Handling of the Attenuation Value - 46 - CXD3003R $BX commands This command sets the traverse monitor count. Command Traverse monitor count setting Data 1 Data 2 Data 3 Data 4 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 * When the set number of tracks are counted during fine search, the sled control for the traverse cycle control goes off. * The traverse monitor count is set to monitor the traverse status from the SENS output as COMP and COUT. - 47 - CXD3003R $CX commands Command D23 Servo coefficient setting CLV CTRL ($DX) Data 1 D22 D21 D20 D19 Data 2 D18 D17 D16 Description Gain Gain Gain Gain Gain Gain PCC0 Valid only when DCLV = 1. MDP1 MDP0 MDS1 MDS0 DCLV1 DCLV0 PCC1 Gain CLVS Valid when DCLV = 1 or 0. The spindle servo gain is externally set when DCLV = 1. * CLVS mode gain setting: GCLVS Gain MDS1 0 0 0 0 1 1 Gain MDS0 0 0 1 1 0 0 Gain CLVS 0 1 0 1 0 1 GCLVS -12dB -6dB -6dB 0dB 0dB +6dB Note) When DCLV = 0, the CLVS gain is as follows. When Gain CLVS = 0, GCLVS = -12dB. When Gain CLVS = 1, GCLVS = 0dB. * CLVP mode gain setting: GMDP: GMDS Gain MDP1 0 0 1 Gain MDP0 0 1 0 GMDP -6dB 0dB +6dB Gain MDS1 0 0 1 Gain MDS0 0 1 0 GMDS -6dB 0dB +6dB * DCLV overall gain setting: GDCLV Gain DCLV1 0 0 1 Gain DCLV0 0 1 0 GDCLV 0dB +6dB +12dB Command bit PCC1 0 0 1 1 PCC0 0 1 0 1 Processing The VPCO1 and 2 signals are output. The VPCO1 and 2 pin outputs are high impedance. The VPCO1 and 2 pin outputs are low. The VPCO1 and 2 pin outputs are high. * This command controls the VPCO1 and VPCO2 pin signals. Identical control can be performed for both VPCO1 and VPCO2 output with this setting. However, VPCO2 can also be set to high impedance with the $E command FCSW separately from this setting. - 48 - CXD3003R * Processing for the $CX commands PCC1 and PCC2 and the $EX command FCSW is shown below. Command bit FCSW 0 0 0 0 1 1 1 1 PCC1 0 0 1 1 0 0 1 1 PCC0 0 1 0 1 0 1 0 1 Processing The VPCO1 signal is output and the VPCO2 pin is high impedance. The VPCO1 and 2 pin outputs are high impedance. The VPCO1 pin output is low and the VPCO2 pin is high impedance. The VPCO1 pin output is high and the VPCO2 pin is high impedance. The VPCO1 and 2 signals are output. The VPCO1 and 2 pin outputs are high impedance. The VPCO1 and 2 pin outputs are low. The VPCO1 and 2 pin outputs are high. $DX commands Data 1 Command CLV CTRL D23 DCLV PWM MD D22 TB D21 TP D20 Gain CLVS See "$CX commands". Command bit DCLV PWM MD = 1 DCLV PWM MD = 0 Description Digital CLV PWM mode specified. Both MDS and MDP are used. CLV-W and CAV-W modes cannot be used. Digital CLV PWM mode specified. Ternary MDP values are output. CLV-W and CAV-W modes can be used. Description Bottom hold at a cycle of RFCK/32 in CLVS and CLVH modes. Bottom hold at a cycle of RFCK/16 in CLVS and CLVH modes. Peak hold at a cycle of RFCK/4 in CLVS mode. Peak hold at a cycle of RFCK/2 in CLVS mode. Command bit TB = 0 TB = 1 TP = 0 TP = 1 - 49 - CXD3003R Command CLV CTRL Data 2 D19 VP7 D18 VP6 D17 VP5 D16 VP4 D15 VP3 Data 3 D14 VP2 D13 VP1 D12 VP0 D11 VP CTL1 Data 4 D10 VP CTL0 D9 0 D8 0 Command bit VP0 to 7 The spindle rotational velocity is set. Processing Command bit VPCTL1 0 0 1 1 VPCTL0 0 1 0 1 Processing The setting of VP0 to 7 is multiplied by 1. The setting of VP0 to 7 is multiplied by 2. The setting of VP0 to 7 is multiplied by 3. The setting of VP0 to 7 is multiplied by 4. The above setting should be 0, 0 except for the CAV-W operating mode. The rotational velocity R of the spindle can be expressed with the following equation. R= 256 - n xl 32 R: Relative velocity at normal speed = 1 n: VP0 to 7 setting value l: Multiple by VPCTL0, 1 - 50 - CXD3003R Command bit VP0 to 7 = F0 (H) : VP0 to 7 = E0 (H) : VP0 to 7 = C0 (H) : VP0 to 7 = A0 (H) : VP0 to 7 = 80 (H) : VP0 to 7 = 60 (H) : VP0 to 7 = 40 (H) Description Playback at 1/2 (1, 2) x speed to Playback at 1 (2, 4) x speed to Playback at 2 (4, 8) x speed to Playback at 3 (6, 12) x speed to Playback at (8, 16) x speed to Playback at (10, 20) x speed to Playback at (12, 24) x speed Playback at (14, -) x speed Playback at (16, -) x speed VP0 to 7 = 20 (H) VP0 to 7 = 00 (H) Notes) 1. Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTLS is high. 2. Regarding the values in parentheses, the former ones are for when DSPB = 1 and VPCTL0, 1 = 0, and the latter ones are for when DSPB = 1, VPCTL0 = 1 and VPCTL1 = 0. - 51 - CXD3003R 16 14 12 R - Relative velocity [Multiple] 10 8 DSPB = 1 6 4 2 DSPB = 0 E0 C0 A0 80 60 40 20 00 VP0 to 7 setting value [HEX] When VPCTL0 = VPCTL1 = 0 32 28 24 R - Relative velocity [Multiple] 20 16 DSPB = 1 12 8 4 DSPB = 0 E0 C0 A0 80 60 40 20 00 VP0 to 7 setting value [HEX] When VPCTL0 = 1, VPCTL1 = 0 - 52 - CXD3003R $EX commands Command SPD mode Data 1 D23 CM3 D22 CM2 D21 CM1 D20 D19 Data 2 D18 D17 D16 D15 Data 3 D14 D13 D12 CM0 EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON Command bit CM3 0 1 1 CM2 0 0 0 CM1 0 0 1 CM0 0 0 0 Mode STOP KICK BRAKE Spindle stop mode. Description Spindle forward rotation mode. Spindle reverse rotation mode. Valid only when LPWR = 0 in any mode. Rough servo mode. When the RF-PLL circuit isn't locked, this mode is used to pull the disc rotations within the RFPLL capture range. PLL servo mode. Automatic CLVS/CLVP switching mode. Used for normal playback. 1 1 0 1 1 1 1 1 1 0 1 0 CLVS CLVP CLVA See Timing Charts 1-6 to 1-12. Command bit EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 INV VPCO 0 0 0 0 1 Mode CLV-N CLV-W Description Crystal reference CLV servo. Used for playback in CLV-W mode.1 CAV-W Spindle control with VP0 to 7. CAV-W Spindle control with the external PWM. VCO-C VCO control.2 1 Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode. 2 Fig. 3-3 shows the control flow with the microcomputer software in VCO-C mode. - 53 - CXD3003R Mode DCLV DCLV PWM MD LPWR Command KICK Timing chart 1-6 (a) 1-6 (b) 1-6 (c) 1-7 (a) 1-7 (b) 1-7 (c) 1-8 (a) 1-8 (b) 1-8 (c) 1-9 (a) 1-9 (b) 1-9 (c) 1-10 (a) 1-10 (b) 1-10 (c) 1-11 (a) 1-11 (b) 1-11 (c) 1-12 (a) 1-12 (b) 1-12 (c) 0 0 0 BRAKE STOP KICK CLV-N 1 0 0 BRAKE STOP KICK 1 0 BRAKE STOP KICK 0 CLV-W 1 0 1 BRAKE STOP KICK BRAKE STOP KICK 0 CAV-W 1 0 1 BRAKE STOP KICK BRAKE STOP Mode CLV-N DCLV 1 DCLV PWM MD 0 1 0 LPWR 0 0 0 1 0 Timing chart 1-13 1-14 1-15 1-16 1-17 (EPWM = 0) 1-18 (EPWM = 0) 1-19 (EPWM = 1) 1-20 (EPWM = 1) CLV-W 1 CAV-W 1 0 1 0 1 Note) CLV-W and CAV-W modes support control only by the ternary output of the MDP pin. Therefore, set DCLV to 1 and DCLV PWM MD to 0 in CLV-W and CAV-W modes. - 54 - CXD3003R Command SPD mode Data 4 D11 Gain CAV1 D10 Gain CAV0 D9 FCSW D8 INV NPCO Gain CAV1 0 0 1 1 Gain CAV0 0 1 0 1 Gain 0dB -6dB -12dB -18dB * This sets the gain when controlling the spindle with the phase comparator in CAV-W mode. Command bit FCSW = 0 FCSW = 1 Processing The VPCO2 pin is not used and it is high impedance. The VPCO2 pin is used and the pin signal is the same as VPCO1. - 55 - Timing Chart 1-3 LRCK 48 bit slot WDCK CDROM = 0 Rch 16bit C2 Pointer Lch 16bit C2 Pointer If C2 Pointer = 1, data is NG - 56 - C2 Pointer for lower 8bits C2 Pointer for upper 8bits Rch C2 Pointer Lch C2 Pointer C2PO CDROM = 1 C2 Pointer for lower 8bits C2PO C2 Pointer for upper 8bits CXD3003R Timing Chart 1-4 750ns to 120s 80 81 96 1 2 3 SQCK SQSO CRCF D0 15-bit peak-data Absolute value display, LSB first D1 D2 D3 D4 D5 D6 D13 D14 L/R Sub Q Data See "Sub Code Interface" Peak data L/R flag 2 3 1 2 3 - 57 - 96 clock pulses CRCF R/L Peak data of this section 16 bit 1 WFCK 96 clock pulses SQCK SQSO L/R CRCF 96 bit data Hold section Level Meter Timing CXD3003R Timing Chart 1-5 1 1 2 3 2 3 WFCK 96 clock pulses 96 clock pulses SQCK - 58 - CRCF Measurement CRCF CRCF Measurement Measurement Peak Meter Timing CXD3003R CXD3003R Timing Chart 1-6 CLV-N mode DCLV = DCLV PWM MD = LPWR = 0 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H MDP L MDP L FSW L FSW L FSW L MON H MON H MON L (a) KICK (b) BRAKE (c) STOP Timing Chart 1-7 CLV-N mode DCLV = 1, DCLV PWM MD = LPWR = 0 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H Z MDP Z L MDP Z FSW L FSW L FSW L MON H MON H MON L (a) KICK (b) BRAKE (c) STOP - 59 - CXD3003R Timing Chart 1-8 CLV-N mode DCLV = DCLV PWM MD = 1, LPWR = 0 KICK H BRAKE STOP MDS MDS L MDS MDP H MDP L H MDP L L FSW L FSW L FSW L MON H MON H MON L (a) KICK (b) BRAKE (c) STOP Timing Chart 1-9 CLV-W mode (when following the spindle rotational velocity) DCLV = 1, DCLV PWM MD = LPWR = 0 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H Z Z MDP L MDP Z FSW L FSW L FSW L MON H MON H MON L (a) KICK Other than when following the velocity, the timing is the same as Timing Chart 1-6 (a). (b) BRAKE Other than when following the velocity, the timing is the same as Timing Chart 1-6 (b). (c) STOP - 60 - CXD3003R Timing Chart 1-10 CLV-W mode (when following the spindle rotational velocity) DCLV = 1, DCLV PWM MD = 0, LPWR = 1 BRAKE STOP KICK MDS Z MDS Z MDS Z MDP H Z MDP Z MDP Z FSW L FSW L FSW L MON H MON H MON L (a) KICK (b) BRAKE (c) STOP Other than when following the velocity, the timing is the same as Timing Chart 1-6 (a). Timing Chart 1-11 CAV-W mode DCLV = 1, DCLV PWM MD = LPWR = 0 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H MDP L MDP Z FSW L FSW L FSW L MON H MON H MON H (a) KICK (b) BRAKE (c) STOP - 61 - CXD3003R Timing Chart 1-12 CAV-W mode DCLV = 1, DCLV PWM MD = 0, LPWR = 1 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H MDP Z MDP Z FSW L FSW L FSW L MON H MON H MON H (a) KICK (b) BRAKE (c) STOP Timing Chart 1-13 CLV-N mode DCLV PWM MD = LPWR = 0 MDS Z n * 236 (ns) n = 0 to 31 Acceleration MDP 132kHz 7.6s Deceleration Z Timing Chart 1-14 CLV-N mode DCLV PWM MD = 1, LPWR = 0 MDS Acceleration MDP 132kHz 7.6s Output Waveforms with DCLV = 1 Deceleration n * 236 (ns) n = 0 to 31 - 62 - CXD3003R Timing Chart 1-15 CLV-W mode DCLV PWM MD = LPWR = 0 MDS Z Acceleration MDP Z Deceleration Output Waveforms with DCLV = 1 132kHz 3.8s Timing Chart 1-16 CLV-W mode DCLV PWM MD = 0, LPWR = 1 MDS Z Acceleration MDP Z 132kHz 3.8s Output Waveforms with DCLV = 1 The BRAKE pulse is masked when LPWR = 1. Timing Chart 1-17 CAV-W mode EPWM = DCLV PWM MD = LPWR = 0 Acceleration MDP Z Deceleration 264kHz 3.8s Timing Chart 1-18 CAV-W mode EPWM = DCLV PWM MD = 0, LPWR = 1 Acceleration MDP Z 264kHz 3.8s The BRAKE pulse is masked when LPWR = 1. - 63 - CXD3003R Timing Chart 1-19 CAV-W mode EPWM = 1, DCLV PWM MD = LPWR = 0 H PWMI L H MDP L Acceleration Deceleration Timing Chart 1-20 CAV-W mode EPWM = 1, DCLV PWM MD = 0, LPWR = 1 H PWMI L H MDP Z Acceleration The BRAKE pulse is masked when LPWR = 1. Note) CLV-W and CAV-W modes support control only by the ternary output of the MDP pin. Therefore, set DCLV PWM MD to 0 in CLV-W and CAV-W modes. - 64 - CXD3003R [2] Subcode Interface There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read out from SBSO by inputting EXCK. Sub Q can be read out after checking CRC of the 80 bits in the subcode frame. Sub Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high. 2-1. P to W Subcode Readout Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.) 2-2. 80-bit Sub Q Readout Fig. 2-2 shows the peripheral block of the 80-bit Sub Q register. * First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit. * 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are loaded into the parallel/serial register. When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC check) has been loaded. * When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first. * Once the 80-bit data load is confirmed, SQCK is input so that the data can be read. The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low. * The retriggerable monostable multivibrator has a time constant from 270 to 400s. When the duration when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register. * While the monostable multivibrator is being reset, data cannot be loaded in the peak detection parallel/serial register or the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by CRCOK and others. * The previously mentioned peak detection register can be connected to the shift-in of the 80-bit parallel/serial register. For ring control 1, input and output are shorted during peak meter and level meter modes. For ring control 2, input and output are shorted during peak meter mode. This is because the register is reset with each readout in level meter mode, and to prevent readout destruction in peak meter mode. As a result, the 96-bit clock must be input in peak meter mode. * The absolute time after peak is stored in the memory in peak meter mode. (See Timing Chart 2-3.) * The high and low intervals for SQCK should be between 750ns and 120s. - 65 - CXD3003R Timing Chart 2-1 Internal PLL clock 4.3218MHz WFCK SCOR EXCK 750ns max SBSO S0 * S1 Q R WFCK SCOR EXCK SBSO S0*S1 Q R S T U V W S0*S1 P1 QRST UVW P1 P2 P3 Same Same Subcode P.Q.R.S.T.U.V.W Read Timing - 66 - Block Diagram 2-2 (ASEC) (AMIN) ADDRS CTRL (AFRAM) SUBQ SIN 80 bit S/P Register ABCDEFGH 8 Order Inversion 8 8 8 8 8 8 8 8 HG F EDC B A 80 bit P/S Register SI SO LD LD LD LD LD LD LD SUBQ LD - 67 - CRCC Monostable multivibrator SHIFT LOAD CONTROL SO 16 bit P/S register SI 16 Peak detection ABS time load control for peak value SHIFT SQCK Ring control 1 Ring control 2 CRCF Mix SQSO CXD3003R Timing Chart 2-3 1 91 95 96 97 98 1 3 2 92 93 94 2 3 WFCK SCOR Determined by mode CRCF1 80 or 96 Clock CRCF2 SQSO CRCF1 SQCK Register load forbidder - 68 - 750ns to 120s 270 to 400s when SQCK = high. ADR0 ADR1 ADR2 ADR3 CTL0 300ns max Monostable Multivibrator (Internal) SQCK SQSO CRCF CTL1 CTL2 CTL3 CXD3003R Timing Chart 2-4 Example: $802000 latch Set SQCK high during this interval. XLAT 750ns or more Internal signal latch SQCK SQSO PER5 PER6 PER7 C1F0 C1F1 C1F2 C2F0 C2F1 C2F2 FOK GFS LOCK EMPH ALOCK VF0 VF1 VF2 VF3 VF4 VF5 PER0 PER1 PER2 PER3 PER4 VF6 VF7 VF8 VF9 Signal Description PER0 to 7 RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB. FOK Focus OK GFS High when the frame sync and the insertion protection timing match. - 69 - Description C1 pointer reset C1 pointer reset C2F2 0 0 0 0 C1 pointer set C1 pointer set 1 1 1 1 C2F1 0 0 1 1 0 0 1 1 C2F0 0 1 0 1 0 1 0 1 -- -- LOCK GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. EMPH High when the playback disc has emphasis. ALOCK GFS is sampled at 460Hz; when GFS is high eight consecutive samples, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. VF0 to 9 Used in CAV-W mode. The result obtained by measuring the rotational velocity of the disc. (See Timing Chart 2-5.) VF0 = LSB, VF7 = MSB. Description No C2 errors; One C2 error corrected; Two C2 errors corrected; C2 pointer reset C2 pointer reset C2 pointer reset Three C2 errors corrected; C2 pointer reset Four C2 errors corrected; C2 pointer reset -- C2 correction impossible; C1 pointer copy C2 correction impossible; C2 pointer set C1F2 C1F1 C1F0 0 0 0 No C1 errors; 0 0 1 One C1 error corrected; 0 1 0 0 1 1 1 0 0 No C1 errors; 1 0 1 One C1 error corrected; 1 1 0 Two C1 errors corrected; C1 pointer set CXD3003R 1 1 1 C1 correction impossible; C1 pointer set CXD3003R Timing Chart 2-5 Measurement interval (approximately 3.8s) Reference window (132.2kHz) Measurement pulse (V16M/2) Measurement counter Load VF0 to 9 m The relative velocity of the disc can be obtained with the following equation. R= m+1 (R: Relative velocity, m: Measurement results) 32 VF0 to 9 is the result obtained by counting VLKI/2 pulses while the reference signal (132.2kHz) generated from XTAL (XTLI, XTLO) (384Fs) is high. This value is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low). - 70 - CXD3003R [3] Description of Modes This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations for each mode are described below. 3-1. CLV-N Mode This mode is compatible with the CXD2510Q, and operation is the same as for conventional control (however, variable pitch cannot be used). The PLL capture range is 150kHz. 3-2. CLV-W Mode This is the wide capture range mode. This mode allows PLL to follow the rotational velocity of the disc. This rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle is the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below. (When using an external VCO, input the signal from the VPCO pin to the low-pass filter, use the output from the low-pass filter as the control voltage for the external VCO, and input the oscillation from the VCO to the VCKI pin.) When starting to rotate the disc and/or speeding up to the lock range from the condition where the disc is stopped, CAV-W mode should be used. Specifically, first send $E665X to set CAV-W mode and kick the disc, then send $E60CX to set CLV-W mode if ALOCK is high, which can be read out serially from the SQSO pin. CLV-W mode can be used while ALOCK is high. The microcomputer monitors the serial data output, and must return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow according to the microcomputer software in CLV-W mode is shown in Fig. 3-2. In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set high, deceleration pulses are not output, thereby achieving low power consumption mode. CLV-W mode supports control only by the ternary output of the MDP pin. Therefore, when using CLV-W mode, set DCLV PWM MD to low. Note) The capture range for this mode is theoretically up to the signal processing limit. 3-3. CAV-W Mode This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to the desired rotational velocity. The rotational velocity is determined by the VP0 to 7 setting values or the external PWM. When controlling the spindle with VP0 to 7, setting CAV-W mode with the $E665X command and controlling VP0 to 7 with the $DX commands allows the rotational velocity to be varied from low speed to 20x speed. (See "$DX commands".) Also, when controlling the spindle with the external PWM, the PWMI pin is binary input which becomes KICK during high intervals and BRAKE during low intervals. The microcomputer can know the rotational velocity using V16M. The reference frequency for the velocity measurement is a signal of 132.3kHz obtained by dividing XTAL (XTLI, XTLO) (384Fs) by 128. The velocity is obtained by counting V16M/2 pulses while the reference is high, and the result is output from the new CPU interface as 10 bits (VP0 to 9). These measurement results are 31 when the disc is rotating at normal speed or 127 when it is rotating at quadruple speed. These values match those of the 256 - n for control with VP0 to 7. (See Table 2-5 and Fig. 2-6.) In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other output signals from this LSI change according to the rotational velocity of the disc. Note) The capture range for this mode is theoretically up to the signal processing limit. Note) Set FLFC to 1 for this mode - 71 - CXD3003R 3-4. VCO-C Mode This is the VCO control mode. In this mode, the V16M oscillation frequency can be controlled by setting VP0 to 7, VPCTL0 and 1 of $D. 1 (256 - n) 32 n: Setting value of VP0 to 7 1: Setting value of VPCTL0 and 1 V16M = V16M determines the VCO1 oscillation frequency. The VCO1 frequency can be expressed with the following equations. * DSPB = 0 VCO1 = V16M x * DSPB = 1 VCO1 = V16M x 49 16 49 24 CAV-W Rotational velocity CLVS Target speed CLV-W CLVP Operation mode Spindle mode KICK Time LOCK ALOCK Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode - 72 - CXD3003R CLV-W Mode CLV-W MODE START KICK $E8000 Mute OFF $A00XXXX CAV-W $E665X (CLVA) NO ALOCK = H ? YES CLV-W $E6C00 (CLVA) (WFCK PLL) YES ALOCK = L ? NO Fig. 3-2. CLV-W Mode Flow Chart VCO-C Mode Access START R? (What minutes for absolute time?) n? (Calculates n) What multiple speed is this equivalent to at arrival? Calculates VP0 to 7. Transfer $E00510 Switches to VCO control mode. EPWM = SPDC = ICAP = SFSL = VC2C = LPWR = 0, HIFC = VPON = 1 Transfer $DX XX Transfers VP0 to 7. ( equivalent to VP0 to 7) Track Jump Subroutine Switches to normal-speed playback mode. EPWM = SFSL = VC2C = LPWR = 0, SPDC = ICAP = HIFC = VPON = 1 Transfer $E66500 Access END Fig. 3-3. Access Flow Chart Using VCO Control - 73 - CXD3003R [4] Description of Other Functions 4-1. Channel Clock Regeneration by the Digital PLL Circuit * The channel clock is necessary for demodulating the EFM signal regenerated by the optical system. Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, a PLL is necessary for regenerating the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses. The block diagram of this PLL is shown in Fig. 4-1. The CXD3003R has a built-in three-stage PLL. * The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary; when not using the internal VCO2, external LPF and VCO are necessary. The output of this first-stage PLL is used as a reference for all clocks within the LSI. * The second-stage PLL regenerates the high-frequency clock needed by the third-stage digital PLL. * The third-stage PLL is a digital PLL that regenerates the actual channel clock. * The digital PLL in CLV-N mode has a secondary loop, and is controlled by the primary loop (phase) and the secondary loop (frequency). When FLFC = 1, the secondary loop can be turned off. High frequency components such as 3T and 4T may contain deviations. In such as case, turning the secondary loop off yields better playability. However, in this case the capture range becomes 50kHz. * A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition to the conventional secondary loop. - 74 - CXD3003R Block Diagram 4-1 CLV-W CAV-W Spindle rotation information Selector Clock input 1/2 XTLI XTSL 1/32 VPCO1 to 2 Phase comparator CLV-N 1/2 1/l 1/n CLV-W /CLV-N CAV-W l = 1, 2, 3, 4 (VPCTL0, 1) Microcomputer control 1/K (KSL1, 0) n = 1 to 256 (VP7 to 0) VCOSEL2 LPF VCTL VCO2 V16M 2/1 MUX VPON VCKI Phase comparator 1/M PCO 1/N FILI FILO 1/K (KSL3, 2) CLTV VCO1 Digital PLL RFPLL VCOSEL1 - 75 - CXD3003R 4-2. Frame Sync Protection * In normal-speed playback, a frame sync is recorded approximately every 136s (7.35kHz). This signal is used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability. * In the CXD3003R, window protection and forward protection/backward protection have been adopted for frame sync protection. These functions achieve very powerful frame sync protection. There are two window widths; one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the backward protection counter to 3. Concretely, when the frame sync is being played back normally and then cannot be detected due to scratches, a maximum of 13 frames are inserted. If the frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. In addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately. 4-3. Error Correction * In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed Solomon codes with a minimum distance of 5. * The CXD3003R uses refined super strategy to achieve double correction for C1 and quadruple correction for C2. * In addition, to prevent C2 miscorrection, a C1 pointer is attached to data after C1 correction according to the C1 error status, the playback status of the EFM signal, and the operating status of the player. * The correction status can be monitored externally. See Table 4-2. * When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an average value interpolation was made for the data. MNT3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MNT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MNT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MNT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C2 correction impossible; C2 correction impossible; Table 4-2. - 76 - No C1 errors; One C1 error corrected; Two C1 errors corrected; C1 correction impossible; No C2 errors; One C2 error corrected; Two C2 errors corrected; Three C2 errors corrected; Four C2 errors corrected; No C1 errors; One C1 error corrected; Description C1 pointer reset C1 pointer reset -- -- C1 pointer set C1 pointer set C1 pointer set C1 pointer set C2 pointer reset C2 pointer reset C2 pointer reset C2 pointer reset C2 pointer reset -- C1 pointer copy C2 pointer set CXD3003R Timing Chart 4-3 Normal-speed PB 400 to 500ns RFCK t = Dependent on error condition MNT3 C1 correction C2 correction MNT2 MNT1 MNT0 Strobe Strobe 4-4. DA Interface * The CXD3003R has two DA interface modes. a) 48-bit slot interface This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. b) 64-bit slot interface This interface includes 64 cycles of the bit clock within one LRCK cycle, and is LSB first. When LRCK is low, the data is for the left channel. - 77 - Timing Chart 4-4 48-bit Slot Normal-Speed Playback PSSL = L LRCK (44.1K) 6 7 8 9 10 11 12 24 1 2 3 4 5 DA15 (2.12M) WDCK DA16 L14 L13 L12 L11 L10 L9 L8 L7 L6 R0 Lch MSB (15) L5 L4 L3 L2 L1 L0 Rch MSB - 78 - 24 L0 Rch MSB 48-bit Slot Double-Speed Playback LRCK (88.2K) 12 DA15 (4.23M) WDCK DA16 R0 Lch MSB (15) CXD3003R Timing Chart 4-5 64-bit Slot Normal Speed Playback PSSL = L DA12 (44.1K) 6 7 8 9 10 11 12 13 14 15 20 30 31 32 1 2 3 4 5 DA13 (2.82M) DA14 Rch LSB (0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 R15 Lch LSB - 79 - 10 15 20 25 30 31 32 Rch LSB (0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lch LSB 64-Bit Slot Double- Speed Playback DA12 (88.2K) 1 2 3 4 5 DA13 (5.64M) DA14 L15 CXD3003R CXD3003R 4-5. Digital Out There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD3003R supports type 2 form 1. The channel status clock accuracy is automatically set to level II when using the crystal clock and to level III in CAV-W mode. In addition, Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bits 0 to 3). DOUT is output when the crystal is 34MHz and DSPB is set to 1 with XTSL high in CLV-N or CLV-W mode. Therefore, set MD2 to 0 and turn DOUT off. Digital Out C bit 0 0 ID0 16 0 1 2 3 4 0 5 0 6 0 7 0 8 1 9 0 10 0 11 0 12 0 13 0 14 0 15 0 From sub Q ID1 COPY Emph 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 32 48 0 176 Bits 0 to 3 Sub Q control bits that matched twice with CRCOK Bit 29 VPON: 1 Crystal: 0 Table 4-6. - 80 - CXD3003R 4-6. Servo Auto Sequence This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1-track jump, 2N-track jump, fine search and M-track move are executed automatically. The servo is used in an exclusive manner during the auto sequence execution (when XBUSY = low), so that commands from the CPU are not transferred to the servo, but can be sent to the CXD3003R. In addition, when using the auto sequence, turn the A.SEQ of register 9 on. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100s after that point. This is to prevent the transfer of erroneous data to the servo when XBUSY changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low). In addition, a MAX timer is built into this LSI as a countermeasure against abnormal operation due to external disturbances, etc. When the auto sequence command is sent from the CPU, this command assumes a $4XY format, in which X specifies the command and Y sets the MAX timer value and timer range. If the executed auto sequence command does not terminate within the set timer value, the auto sequence is interrupted (like $40). See [1] "$4X commands" concerning the timer value and range. Also, the MAX timer is invalidated by inputting $4X0. Although this command is explained in the format of $4X in the following command descriptions, the timer value and timer range are actually sent together from the CPU. (a) Auto focus ($47) Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-8. The auto focus starts with focus search-up, and note that the pickup should be lowered beforehand (focus search-down). In addition, blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E. (b) Track jump 1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled servos are on. Note that tracking gain-up and braking-on ($17) should be sent beforehand because they are not involved in this sequence. * 1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 4-9. Set blind A and brake B with register 5. * 10-track jump When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance with Fig. 4-10. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on. - 81 - CXD3003R * 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 4-11. The track jump count N is set with register 7. Although N can be set to 216 tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps when N is less than 16, and MIRR is used with N is 16 or more. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6. * Fine search When $44 ($45 for REV) is received from the CPU, a FWD (REV) fine search (N-track jump) is performed in accordance with Fig. 4-12. The differences from a 2N-track jump are that a higher precision is achieved by controlling the traverse speed, and a longer distance jump achieved by controlling the sled. The track jump count is set with register 7. N can be set to 216 tracks. After kicking the actuator and sled, the traverse speed is controlled based on the overflow G. Set kick D and F with register 6 and overflow G with register 5. Also, sled speed control during traverse can be turned off by causing COMP to fall. Set the number of tracks during which COMP falls with register B. After N tracks have been counted through COUT, the brake is applied to the actuator and sled. (This is performed by turning on the tracking servo for the actuator, and by kicking the sled in the opposite direction during the time for kick D set with register 6.) Then, the tracking and sled servos are turned on. Set overflow G to the speed required to slow up just before the track jump terminates. (The speed should be such that it will come on-track when the tracking servo turns on at the termination of the track jump.) For example, set the target track count N - for the traverse monitor counter which is set with register B, and COMP will be monitored. When the falling edge of this COMP is detected, overflow G can be reset. - 82 - CXD3003R Auto focus Focus search up FOK = H YES NO FZC = H YES NO Check whether FZC is continuously high for the period of time E set with register 5. FZC = L NO YES Focus servo ON END Fig. 4-8-(a). Auto Focus Flow Chart $47 Latch XLAT FOK SEIN (FZC) BUSY Command for SSP $03 Blind E $08 Fig. 4-8-(b). Auto Focus Timing Chart - 83 - CXD3003R 1 Track Track kick sled servo WAIT (Blind A) REV kick for REV jump COUT = YES Track REV kick WAIT (Brake B) Track sled servo ON NO FWD kick for REV jump END Fig. 4-9-(a). 1-Track Jump Flow Chart $48 (REV = $49) Latch XLAT COUT BUSY Blind A Command for SSP $28 ($2C) $2C ($28) Brake B $25 Fig. 4-9-(b). 1-Track Jump Timing Chart - 84 - CXD3003R 10 Track Track, sled FWD kick WAIT (Blind A) Counts COUT x 5 COUT = 5 ? YES Track, REV kick NO Check whether the COUT cycle is longer than overflow C. C = Overflow ? YES Track, sled servo ON NO END Fig. 4-10-(a). 10-Track Jump Flow Chart $4A (REV = $4B) Latch XLAT COUT BUSY Blind A Command for SSP COUT 5 count Overflow C $2A ($2F) $2E ($2B) $25 Fig. 4-10-(b). 10-Track Jump Timing Chart - 85 - CXD3003R 2N Track Track, sled FWD kick WAIT (Blind A) COUT (MIRR) = N Counts COUT for the first 16 times and MIRR for more times. NO YES Track REV kick C = Overflow YES Track servo ON NO WAIT (Kick D) Sled servo ON END Fig. 4-11-(a). 2N-Track Jump Flow Chart $4C (REV = $4D) Latch XLAT COUT (MIRR) BUSY Blind A Command for SSP $2A ($2F) COUT (MIRR) N count $2E ($2B) Overflow C $26 ($27) Kick D $25 Fig. 4-11-(b). 2N-Track Jump Timing Chart - 86 - CXD3003R Fine Search Track Servo ON Sled FWD Kick WAIT (Kick D) Track Sled FWD Kick WAIT (Kick F) Traverse Speed Ctrl (Overflow G) COUT = N ? YES Track Servo ON Sled REV Kick NO WAIT (Kick D) Track Sled Servo ON END Fig. 4-12-(a). Fine Search Flow Chart $44 (REV = $45) latch XLAT COUT BUSY Kick D $26 ($27) Kick F Traverse Speed Control (Overflow G) & COUT N count Kick D $27 ($26) $25 $2A ($2F) Fig. 4-12-(b). Fine Search Timing Chart - 87 - CXD3003R M Track Move Track Servo OFF Sled FWD Kick WAIT (Blind A) COUT (MIRR) = M Counts COUT for M < 16. Counts MIRR for M 16. NO YES Track, Sled Servo OFF END Fig. 4-13-(a). M-Track Move Flow Chart $4E (REV = $4F) Latch XLAT COUT (MIRR) BUSY Blind A Command for servo $22 ($23) COUT (MIRR) M count $20 Fig. 4-13-(b). M-Track Move Timing Chart - 88 - CXD3003R 4-7. Digital CLV Fig. 4-14 shows the block diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes. In addition, the digital spindle servo gain is variable. Digital CLV CLVS U/D MDS Error MDP Error Measure Measure CLV P/S 2/1 MUX Over Sampling Filter-1 Gain MDP 1/2 Mux Gain MDS Gain DCLV Over Sampling Filter-2 CLV P/S Noise Shape KICK, BRAKE, STOP Modulation PWMI DCLVMD, LPWR Mode Select MDS MDP CLVS U/D : MDS error: MDP error: PWMI: Up/down signal from CLVS servo Frequency error for CLVP servo Phase error for CLVP servo Spindle drive signal from the microcomputer for CAV servo Fig. 4-14. Block Diagram - 89 - CXD3003R 4-8. Playback Speed In the CXD3003R, the following playback modes can be selected through different combinations of XTLI, XTSL pin, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency division commands (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode. Mode 1 2 3 4 5 6 7 XTLI 768Fs 768Fs 768Fs 768Fs 384Fs 384Fs 384Fs XTSL 1 1 0 0 0 0 1 DSPB 0 1 0 1 0 1 1 VCOSEL11 0/1 0/1 1 1 0/1 0/1 0/1 ASHS 0 0 1 1 0 0 0 Playback speed 1x 2x 2x 4x 1x 2x 1x Error correction C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double 1 Actually, the optimal value should be used together with KSL3 and KSL2. The playback speed can be varied by setting VP0 to 7 in CAV-W mode. See "3. Description of Modes" for details. - 90 - CXD3003R 4-9. DAC Block Playback Speed * The DAC block playback speed is controlled by sending the DADS command to the DSP block. Mode 1 2 X'tal 768fs 384fs DADS 0 1 4-10. DAC Block Input Timing The DAC input timing chart is shown below. Audio data is not transferred from the CD signal processor block to the DAC block inside the CXD3003R. This is to allow data to be sent to the DAC block via the audio DSP, etc. When the data is input to the DAC block without using the audio DSP, the data must be connected outside the LSI. In this case, LRCK, BCK and PCMD can be connected directly with LRCKI, BCKI and PCMDI, respectively. (See the Application Circuit.) Normal-Speed Playback LRCKI (44.1k) 1 BCKI (2.12M) PCMDI Invalid L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 - 91 - CXD3003R 4-11. Asymmetry Compensation Fig. 4-15 shows the block diagram and circuit example. CXD3003R 22 ASYE ASYO R1 RFAC 14 R1 17 R2 R1 ASYI 16 R1 BIAS 15 R1 2 = R2 5 Fig. 4-15. Asymmetry Compensation Application Circuit. - 92 - CXD3003R 4-12. CXD3003R Clock System The DAC, digital signal processor and digital servo blocks can be switched to each playback mode according to how the crystal and clock circuit are connected. Each circuit is as shown in the diagram below; during normal use, FSTO and FSTI are directly connected to each other. XTLI 384fs or 768fs XTLO OSC 1/2 Clock supplied to DAC 384fs To DAC block DADS (command register) MCKO To exterior 1/2 XTSL To CD signal processor block 2/3 FSTO External connection FSTI 1/2 To digital servo block 1/4 XT1D XT2D XT4D (command register) - 93 - CXD3003R [5] Description of Servo Signal Processing System Functions and Commands 5-1. General Description of the Servo Signal Processing System (VDD: Supply voltage) Focus servo Sampling rate: 88.2kHz (when MCK = 128Fs) Input range: 1/4VDD to 3/4VDD Output format: 7-bit PWM Other: Offset cancel Focus bias adjustment Focus search Gain-down function Defect countermeasure Auto gain control Tracking servo Sampling rate: Input range: Output format: Other: 88.2kHz (when MCK = 128Fs) 1/4VDD to 3/4VDD 7-bit PWM Offset cancel E:F balance adjustment Track jump Gain-up function Defect countermeasure Drive cancel Auto gain control Vibration countermeasure Sled servo Sampling rate: Input range: Output format: Other: 345Hz (when MCK = 128Fs) 1/4VDD to 3/4VDD 7-bit PWM Sled move FOK, MIRR, DFCT signal generation RF signal sampling rate: 1.4MHz (when MCK = 128Fs) Input range: 1/4VDD to 3/4VDD Other: RF zero level automatic measurement - 94 - CXD3003R 5-2. Digital Servo Block Master Clock (MCK) The FSTI pin is the reference clock input pin. The internal master clock (MCK) is generated by dividing the frequency of the signal input to FSTI. The frequency division ratio is 1, 1/2 or 1/4. Table 5-1 below assumes that the crystal clock generated from the digital signal processor block which is 2/3 frequency-divided of XTLI is input to the FSTI pin by externally connecting the FSTI pin and the FSTO pin. The XT4D and XT2D command can be set with D13 and D12 of $3F, and the XT1D command can be set with D1 of $3E. (Default = 0) The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical. Mode 1 2 3 4 5 6 7 XTLI 384Fs 384Fs 384Fs 768Fs 768Fs 768Fs 768Fs FSTO (FSTI) 256Fs 256Fs 256Fs 512Fs 512Fs 512Fs 512Fs XTSL 0 1 XT4D 0 1 0 XT2D 1 0 1 0 0 XT1D 1 0 0 1 0 0 0 Frequency division ratio 1 1/2 1/2 1 1/2 1/4 1/4 MCK 256Fs 128Fs 128Fs 512Fs 256Fs 128Fs 128Fs Fs = 44.1kHz, : Don't care Table 5-1. 5-3. AVRG (Average) Measurement and Compensation The CXD3003R has a circuit that measures AVRG of RFDC, VC, FE and TE and a circuit that compensates these signals to control the servo effectively. AVRG measurement and compensation is necessary to initialize the CXD3003R, and is able to cancel the offset. The level applied to the VC, FE, RFDC and TE pins can be measured by setting D15 (VCLM), D13 (FLM), D11 (RFLM) and D4 (TCLM) of $38 respectively to 1. AVRG measurement takes the level applied to each analog input pin as the average of 256 samples, and then loads each value into the AVRG register. AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is received. During AVRG measurement, if the upper 8 bits of the command register are 38 (Hex), the completion of AVRG measurement operation can be confirmed through the SENS pin. (See Timing Chart 5-2.) XLAT 2.9 to 5.8ms SENS (= XAVEBSY) AVRG measurement completed Max. 1s Timing Chart 5-2. - 95 - CXD3003R - 96 - CXD3003R 5-4. E:F Balance Adjustment Function When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search), the traverse waveform appears in the TE signal due to disc eccentricity. In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold filter by setting D5 (TBLM) of $38 to 1. The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC register value is established when TBLM returns to 0. Next, setting D2 (TLC2) of $38 to 1 compensates TE and SE values with the TRVSC register value (subtraction), resulting the E:F balance offset to be adjusted. (See Fig. 5-3.) 5-5. FCS Bias (Focus Bias) Adjustment Function The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See Fig. 5-3.) When the FBIAS register value is set when D11 = 0 and D10 = 1 with $34F, data can be written using the 9-bit value of D9 to D1 (D9: MSB). In addition, the RF jitter can be monitored by setting the SOCT command of $8 to 1. (See "DSP Block Timing Chart".) The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. The FBIAS register functions as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0. The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A. When using the FBIAS register as a counter, the counter stops if the FBIAS value the value set beforehand in FLB9 to 1 of $34 matches. Also, if the upper 8 bits of the command register are $3A at this time, the counter stop can be monitored through SENS. Here, assume the FBIAS setting value FB9 to 1 and the FBIAS LIMIT value FBL9 to 1 like status A. For example, if command registers FBUP = 0, FBV1 = 0, FBV0 = 0 and FBSS = 1 are set from this status, down count starts from status A and approaches the set LIMIT value. When the FBIAS value matches FBL9 to 1, the counter stops and the SENS pin goes to high. Note that the up/down counter counts at each sampling cycle of the focus servo filter. The number of steps by which the count value changes can be selected from 1, 2, 4 or 8 steps by FBV1 and FBV0. When converted to FE input, 1 step corresponds to 1/512 x VDD/2. A: Register mode B: Counter mode C: Counter mode (when stopped) A B C FBIAS setting value (FB9 to 1) LIMIT value (FLB9 to 1) SENS pin - 97 - RFDC from A/D RF AVRG register RFLC - To RF In register SE from A/D - TLC0 * TLD0 TLC1 * TLD1 TLC2 * TLD2 - - To SLD In register TE from A/D - - - To TRK In register TLC0 VC AVRG register TE AVRG register TLC1 TRVSC register TLC2 - 98 - VCLC - FE AVRG register FLC1 - FBIAS register FBON FLC0 - FE from A/D To FCS In register To FZC register CXD3003R Fig. 5-3. CXD3003R 5-6. AGCNTL (Automatic Gain Control) Function The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate gain with the servo loop. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but also obtains the optimal gain for each disc. The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of the command register are 38 (Hex), the completion of AGCNTL operation can be confirmed through the SENS pin. (See Timing Chart 5-4 and "Description of SENS Signals".) Setting D9 and D8 of $38 to 1 set FCS (focus) and TRK (tracking) respectively to AGCNTL operation. Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described hereafter) must be disabled. XLAT Max. 11.4s SENS (= AGOK) AGCNTL completion Timing Chart 5-4. Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking AGCNTL) due to AGCNTL. These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written externally. After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from the SENS pin with the serial readout function (described hereafter). AGCNTL related settings The following settings can be changed with $35, $36 and $37. FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (Hex) TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (Hex) AGS; Self-stop on/off AGJ; Convergence completion judgment time AGGF; Internally generated sine wave amplitude (AGF) AGGT; Internally generated sine wave amplitude (AGT) AGV1; AGCNTL sensitivity 1 (during rough adjustment) AGV2; AGCNTL sensitivity 2 (during fine adjustment) AGHS; Rough adjustment on/off AGHT; Fine adjustment time Note) Converging servo loop gain values can be changed with the FG6 to 0 and TG6 to 0 setting values. In addition, these setting values must be within the effective setting range. The default settings aim for 0 dB at 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary. - 99 - CXD3003R AGCNTL and default operation have two stages. In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select 256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value. The sensitivity at this time can be selected from two types with AGV1. In the second stage, the AGCNTL coefficient is finely adjusted to approach more appropriate value with relatively low sensitivity. The sensitivity for the second stage can be selected from two types with AGV2. In the second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops changing, the CXD3003R confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self-stop mode) This self-stop mode can be canceled by setting AGS to 0. In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0. An example of AGCNTL coefficient transitions during AGCNTL in various settings are shown in Fig. 5-5. Initial value Slope AGV1 AGCNTL coefficient value Slope AGV2 Convergence value AGHT AGCNTL Start SENS AGJ AGCNTL completion Fig. 5-5. - 100 - CXD3003R 5-7. FCS Servo and FCS Search (Focus Search) The FCS servo is controlled by the 8-bit serial command $0X. (See Table 5-6.) Register name Command D23 to D20 D19 to D16 10 11 0 FOCUS CONTROL 0000 00 01 010 011 FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP : Don't care Table 5-6. FCS Search FCS search is required in the course of turning on the FCS servo. Fig. 5-7 shows the signals for sending commands $00 $02 $03 and performing only FCS search operation. Fig. 5-8 shows the signals for sending $08 (FCS on) after that. $00 $02 $03 $00 $02 $03 $08 0 FCSDRV FCSDRV RF FOK FZC comparator level FE 0 RF FOK FE 0 FZC FZC Fig. 5-7. Fig. 5-8. - 101 - CXD3003R 5-8. TRK (Tracking) and SLD (Sled) Servo Control The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 5-9.) When the upper 4 bits of the command register are 2 (Hex), TZC is output to the SENS pin. Register name Command D23 to D20 D19 to D16 00 01 10 2 TRACKING MODE 0010 11 00 01 10 11 TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE : Don't care Table 5-9. TRK Servo The TRK JUMP (track jump) level can be set with 6 bits (D13 to D8) of $36. In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter switches to gain-up mode. The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the anti-shock circuit (described hereafter) enabled. CXD3003R has 2 types of filters in TRK gain-up mode which can be selected by setting D16 of $1. (See Table 5-17.) SLD Servo The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by multiplying this value by 1x, 2x, 3x or 4x magnification set using D17 and D16 when D18 = D19 = 0 is set with $3. (See Table 5-10.) SLD MOV must be performed continuously for 50s or more. In addition, if the LOCK input signal goes low when the SLD servo is on, the SLD servo turns off. Note) When the LOCK signal is low, the TRK servo switches to gain-up mode and the SLD servo is turned off by the default. These operations are disabled by setting D6 (LKSW) of $38 to 1. Register name Command D23 to D20 D19 to D16 0000 3 SELECT 0011 0001 0010 0011 SLED KICK LEVEL (basic value x 1) SLED KICK LEVEL (basic value x 2) SLED KICK LEVEL (basic value x 3) SLED KICK LEVEL (basic value x 4) Table 5-10. - 102 - CXD3003R 5-9. MIRR and DFCT Signal Generation The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and loaded. The MIRR and DFCT signals are generated from this RF signal. MIRR Signal Generation The loaded RF signal is applied to peak hold and bottom hold circuits. An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is generated from the average of this envelope waveform. The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value from the peak hold value with this MIRR comparator level. (See Fig. 5-11.) The bottom hold speed and mirror sensitivity can be selected from 4 values using D7 and 6, and D5 and 4, respectively, of $3C. RF Peak Hold Bottom Hold Peak Hold - Bottom Hold MIRR Comp (Mirror comparator level) H MIRR L Fig. 5-11. DFCT Signal Generation The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is generated by comparing the difference between these two peak hold waveforms with the DFCT comparator level. (See Fig. 5-12.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B. RF Peak Hold1 Peak Hold2 Peak Hold2 - Peak Hold1 SDF (Defect comparator level) H DFCT L Fig. 5-12. - 103 - CXD3003R 5-10. DFCT Countermeasure Circuit The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not become easily dislocated due to scratches or defects on discs. Specifically, these operations are achieved by detecting scratch and defect with the DFCT signal generation circuit, and when DFCT goes high, applying the low frequency element of the error signal before DFCT went high to the FCS and TRK servo filter inputs. (See Fig. 5-13.) In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38 to 1. Hold Filter Error signal Input register DFCT Hold register EN Servo Filter Fig. 5-13. 5-11. Anti-Shock Circuit When vibrations occurs in the CD player, this circuit forces the TRK filter to switch to gain-up mode so that the servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures. Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is increased. (See Fig. 5-14.) The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator level is practically variable by adjusting the value of the anti-shock filter output coefficient K35. This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See Table 5-17.) This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up mode by inputting high level to the ATSK pin. When the upper 8 bits of the command register are $1, vibration detection can be monitored from the SENS pin. ATSK TE Anti Shock Filter Comparator SENS TRK Gain Up Filter TRK Gain Normal Filter TRK PWM Gen Fig. 5-14. - 104 - CXD3003R 5-12. Brake Circuit Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to turn on. The brake circuit prevents these phenomenon. The brake circuit is to use tracking drive as a brake by cutting unnecessary portions of it utilizing the 180 offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 5-15 and 5-16.) Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal. The brake circuit can be turned on and off by D18 of $1. (See Fig. 5-17.) Inner track Outer track Outer track Inner track FWD REV Servo ON JMP JMP TRK DRV TRK DRV REV FWD Servo ON JMP JMP RF Trace MIRR TE TZC Edge TRKCNCL TRK DRV SENS TZC out 0 0 RF Trace MIRR TE TZC Edge TRKCNCL TRK DRV SENS TZC out 0 0 Fig. 5-15. Fig. 5-16. Register name Command D23 to D20 D19 to D16 10 0 1 0 0 1 1 0 ANTI SHOCK ON ANTI SHOCK OFF BRAKE ON BRAKE OFF TRACKING GAIN NORMAL TRACKING GAIN UP TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP FILTER SELECT 2 : Don't care Fig. 5-17. - 105 - 1 TRACKING CONTROL 0001 CXD3003R 5-13. COUT Signal The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by loading the MIRR signal at both edges of the TZC signal. And the used TZC signal can be selected among three different phases for each COUT signal application. * HPTZC: For 1-track jumps Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced by a cut-off 1kHz digital HPF; when MCK = 128Fs.) * STZC: For COUT signal generation when MIRR is externally input and for applications other than COUT generation. This is generated from sampling TE at 700kHz. (when MCK = 128Fs) * DTZC: For High-speed traverse Reliable COUT signal generation with a delayed phase STZC signal. Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance with the MIRR signal delay during high-speed traverse. The COUT signal output method is switched with D15 and 14 of $3. When D15 = 1 : STZC When D15 = 0 and D14 = 0 : HPTZC When D15 = 0 and D14 = 1 : DTZC When the DTZC is selected, the delay can be selected from two values with D14 of $36. 5-14. Serial Readout Circuit The following measurement and adjustment results can be read out from the SENS pin by inputting the readout clock to the SCLK pin by $39. (See Fig. 5-18, Table 5-19 and "Description of SENS Signals".) Specified commands $390C: VC AVRG measurement result $3908: FE AVRG measurement result $3904: TE AVRG measurement result $391F: RF AVRG measurement result $3953: FCS AGCNTL coefficient result $3963: TRK AGCNTL coefficient result $391C: TRVSC adjustment result $391D: FBIAS register value XLAT tDLS tSPW SCLK 1/fSCLK Serial Read Out Data (SENS) *** MSB *** LSB Fig. 5-18. Item SCLK frequency SCLK pulse width Delay time Symbol fSCLK Min. Typ. Max. 16 31.3 15 Unit MHz ns s tSPW tDLS Table 5-19. During readout, the upper 8 bits of the command register must be 39 (Hex). - 106 - CXD3003R 5-15. Writing to the Coefficient RAM The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and transfer from the ROM to the RAM is completed approximately 40s (when MCK = 128Fs) after the XRST pin rises. (The coefficient RAM cannot be rewritten during this period.) After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address of the coefficient RAM. The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and D7 to D0 as data. Coefficient rewriting is completed 11.3s (when MCK = 128Fs) after the command is received. When rewriting multiple coefficients, be sure to wait 11.3s (when MCK = 128Fs) before sending the next rewrite command. 5-16. PWM Output FCS, TRK and SLD outputs are output as PWM waveforms. In particular, FCS and TRK permit accurate drive by using a double oversampling noise shaper. Timing Chart 5-20 and Fig. 5-21 show examples of output waveforms and drive circuits. MCK (5.6448MHz) Output value +A SLD 64tMCK SFDR SRDR AtMCK AtMCK 64tMCK 64tMCK Output value -A Output value 0 FCS/TRK 32tMCK FFDR/ TFDR FRDR/ TRDR A tMCK 2 32tMCK A tMCK 2 A tMCK 2 A tMCK 2 32tMCK 32tMCK 32tMCK 32tMCK tMCK = 1 180ns 5.6448MHz Timing Chart 5-20. - 107 - CXD3003R Example of Drive Circuit VCC 22k 22k RDR FDR 22k 22k DRV VEE Fig. 5-21. Operational Amplifier Drive Circuit - 108 - CXD3003R 5-17. DIRC Input Pin The $2 command register can be changed by operating the DIRC input pin. Using the DIRC pin simplifies serial data transfer during TRKJMP. Fig. 5-22 shows $2 command register changes produced by DIRC pin changes. Also, Timing Chart 5-23 shows DIRC-based operations during TRKJMP. High level must be input to the DIRC pin when the XRST pin rises from low to high. DIRC Q3 0 TRK 0 1 1 Q2 0 1 0 1 Servo status OFF ON FWD JMP REV JMP Q3 1 1 1 1 Q2 1 0 1 0 Servo status REV JMP FWD JMP REV JMP FWD JMP Q3 0 0 0 0 Q2 1 1 1 1 Servo status ON ON ON ON Q1 0 SLD 0 1 1 Q0 0 1 0 1 Servo status OFF ON FWD MOV REV MOV Q1 0 0 1 1 Q0 0 1 0 1 Servo status OFF ON FWD MOV REV MOV Q1 0 0 1 1 Q0 1 1 0 1 Servo status ON ON FWD MOV REV MOV Q3, Q2, Q1 and Q0 correspond to D19, D18, D17 and D16 of $2. Fig. 5-22. $28 latch $2C latch XLAT DIRC FWD JUMP REV JUMP TRK SERVO SLD SERVO ON OFF ON OFF ON OFF ON OFF Timing Chart 5-23. - 109 - CXD3003R 5-18. Servo Status Changes Produced by the LOCK Signal When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off in order to prevent SLD free-running. Setting D6 (LKSW) of $38 to 1 deactivates this function. In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low. This enables microcomputer control. 5-19. Description of Commands and Data Sets The following description contains portions which convert internal voltages into the values when they are output externally and describe them as input conversion or output conversion. Input conversion converts these voltages into the voltages entering input pins before A/D conversion. Output conversion converts PWM output values into analog voltage values. - 110 - CXD3003R $34 D15 0 D14 KA6 D13 KA5 D12 KA4 D11 KA3 D10 KA2 D9 KA1 D8 KA0 D7 KD7 D6 KD6 D5 KD5 D4 KD4 D3 KD3 D2 KD2 D1 KD1 D0 KD0 When D15 = 0 KA6 to KA0: Coefficient address KD7 to KD0: Coefficient data D15 1 D14 1 D13 1 D12 1 D11 1 D10 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 -- FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 When D15 = D14 = D13 = D12 = D11 = 1 ($34F) D10 = 0 FBIAS LIMIT register write FBL9 to FBL1: Data; data compared with FB9 to 1, FBL9 = MSB. When using the FBIAS register in counter mode, counter operation stops when the value of FB9 to 1 matches with FBL9 to 1. D15 1 D14 1 D13 1 D12 1 D11 0 D10 1 D9 FB9 D8 FB8 D7 FB7 D6 FB6 D5 FB5 D4 FB4 D3 FB3 D2 FB2 D1 FB1 D0 -- When D15 = D14 = D13 = D12 = 1 ($34F) D11 = 0, D10 = 1 FBIAS register write FB9 to FB1: Data; FB9 is MSB two's complement data. For FE input conversion, FB9 to FB1 = 011111111 corresponds to 255/256 x VDD/4 and FB9 to FB1 = 100000000 to -256/256 x VDD/4 respectively. (VDD: supply voltage) D15 1 D14 1 D13 1 D12 1 D11 0 D10 0 D9 TV9 D8 TV8 D7 TV7 D6 TV6 D5 TV5 D4 TV4 D3 TV3 D2 TV2 D1 TV1 D0 TV0 When D15 = D14 = D13 = D12 = 1 ($34F) D11 = 0, D10 = 0 TRVSC register write TV9 to TV0: Data; TV9 is MSB two's complement data. For TE input conversion, TV9 to TV0 = 0011111111 corresponds to 255/256 x VDD/4 and TV9 to TV0 = 1100000000 to -256/256 x VDD/4 respectively. (VDD: supply voltage) Note) * When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to each bit TV8 to TV0 during external write are read out. * When reading out internally measured values and then writing these values externally, set TV9 the same as TV8. - 111 - CXD3003R $35 (preset: $35 58 2D) D15 FT1 D14 FT0 D13 FS5 D12 FS4 D11 FS3 D10 FS2 D9 FS1 D8 FS0 D7 FTZ D6 FG6 D5 FG5 D4 FG4 D3 FG3 D2 FG2 D1 FG1 D0 FG0 FT1, FT0, FTZ: Focus search-up speed Default value: 010 (0.673 x VDD V/s) Focus drive output conversion FT1 0 0 1 1 0 0 1 1 FT0 0 1 0 1 0 1 0 1 FTZ 0 0 0 0 1 1 1 1 Focus search speed [V/s] 1.35 x VDD 0.673 x VDD 0.449 x VDD 0.336 x VDD 1.79 x VDD 1.08 x VDD 0.897 x VDD 0.769 x VDD : preset, VDD: PWM driver supply voltage FS5 to FS0: Focus search limit voltage Default value: 011000 (24/64 x VDD, VDD: PWM driver supply voltage) Focus drive output conversion FG6 to FG0: AGF convergence gain setting value Default value: 0101101 $36 (preset: $36 0E 2E) D15 D14 D13 D12 TJ4 D11 TJ3 D10 TJ2 D9 TJ1 D8 D7 D6 D5 TG5 D4 TG4 D3 TG3 D2 TG2 D1 TG1 D0 TG0 TDZC DTZC TJ5 TDZC: TJ0 SFJP TG6 Selects the TZC signal for generating the TRKCNCL signal during brake circuit operation. TDZC = 0: the edge of the HPTZC or STZC signal, whichever has the faster phase, is used. TDZC = 1: the edge of the HPTZC or STZC signal or the tracking drive signal zero-cross, whichever has the faster phase, is used. (See 5-12.) DTZC: DTZC delay (8.5/4.25s, when MCK = 128Fs) Default value: 0 (4.25s) TJ5 to TJ0: Track jump voltage Default value: 001110 ( 14/64 x VDD, VDD: PWM driver supply voltage) Tracking drive output conversion SFJP: Surf jump mode on/off The tracking PWM output is made by adding the tracking filter output and TJReg (TJ5 to 0), by setting D7 to 1 (on) TG6 to TG0: AGT convergence gain setting value Default value: 0101110 - 112 - CXD3003R $37 (preset: $37 50 BA) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT FZSH, FZSL: FZC (Focus Zero Cross) slice level Default value: 01 (1/8 x VDD/2, VDD: supply voltage); FE input conversion FZSH 0 0 1 1 FZSL 0 1 0 1 Slice level 1/4 x VDD/2 1/8 x VDD/2 1/16 x VDD/2 1/32 x VDD/2 : preset SM5 to SM0: Sled move voltage Default value: 010000 ( 16/64 x VDD, VDD: PWM driver supply voltage) Sled drive output conversion AGS: AGCNTL self-stop on/off Default value: 1 (on) AGJ: AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms, when MCK = 128Fs) Default value: 0 (63ms) AGGF: Focus AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) AGGT: Tracking AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) FE/TE input conversion AGGF AGGT 0 (small) 1 (large) 0 (small) 1 (large) 1/32 x VDD/2 1/16 x VDD/2 1/16 x VDD/2 1/8 x VDD/2 : preset AGV1: AGV2: AGHS: AGHT: AGCNTL convergence sensitivity during high sensitivity adjustment; high/low Default value: 1 (high) AGCNTL convergence sensitivity during low sensitivity adjustment; high/low Default value: 0 (low) AGCNTL high sensitivity adjustment on/off Default value: 1 (on) AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs) Default value: 0 (256ms) - 113 - CXD3003R $38 (preset: $38 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFS LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 VCLM: VCLC: FLM: FLC0: RFLM: RFLC: AGF: AGT: DFSW: LKSW: TBLM: TCLM: FLC1: TLC2: TLC1: TLC0: VC level measurement (on/off) VC level compensation for FCS In register (on/off) Focus zero level measurement (on/off) Focus zero level compensation for FZC register (on/off) RF zero level measurement (on/off) RF zero level compensation (on/off) Focus auto gain adjustment (on/off) Tracking auto gain adjustment (on/off) Defect disable switch (on/off) Setting this switch to 1 (on) disables the defect countermeasure circuit. Lock switch (on/off) Setting this switch to 1 (on) disables the sled free-running prevention circuit. Traverse center measurement (on/off) Tracking zero level measurement (on/off) Focus zero level compensation for FCS In register (on/off) Traverse center compensation (on/off) Tracking zero level compensation (on/off) VC level compensation for TRK/SLD In register (on/off) Note) Commands marked with are accepted every 2.9ms. (when MCK = 128Fs) All commands are on when set to 1. - 114 - CXD3003R $39 D15 D14 D13 SD5 D12 SD4 D11 SD3 D10 SD2 D9 SD1 D8 SD0 DAC SD6 DAC: Serial data readout DAC mode (on/off) SD6 to SD0: Serial readout data select SD6 1 0 SD5 Readout data Readout data length 8 bit 16 bit Coefficient RAM data for address = SD5 to SD0 1 Data RAM data for address = SD4 to SD0 SD4 SD3 to SD0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 0 RF AVRG register RFDC input signal FBIAS register TRVSC register RFDC envelope (bottom) RFDC envelope (peak) RFDC envelope (peak) - (bottom) VC AVRG register FE AVRG register TE AVRG register FE input signal TE input signal SE input signal VC input signal 1 0 0 8 bit 8 bit 9 bit 9 bit 8 bit 8 bit 8 bit 9 bit 9 bit 9 bit 8 bit 8 bit 8 bit 8 bit $399F $399E $399D $399C $3993 $3992 $3991 $398C $3988 $3984 $3983 $3982 $3981 $3980 0 Note) Coefficients K40 to K4F cannot be read out. : Don't care See the description for SRO1 and SRO0 of $3F concerning readout methods for the above data. - 115 - CXD3003R $3A (preset: $3A 00 00) D15 0 FBON: D14 D13 D12 D11 D10 D9 0 D8 D7 D6 D5 D4 D3 0 D2 D1 D0 FBON FBSS FBUP FBV1 FBV0 TJD0 FPS1 FPS0 TPS1 TPS0 SJHD INBK MTI0 FBIAS (focus bias) register addition (on/off) The FBIAS register value is added to the signal loaded into the FCS In register by FBON = 1 (on). FBSS: FBIAS (focus bias) register/counter switching FBSS = 0: register, FBSS = 1: counter. FBUP: FBIAS (focus bias) counter up/down operation switching This performs counter up/down control when FBSS = 1. FBUP = 0: down counter, FBUP = 1: up counter. FBV1, FBV0: FBIAS (focus bias) counter voltage switching The number of FCS BIAS count-up/-down steps per cycle is decided by these bits. FBV1 0 0 1 1 FBV0 0 1 0 1 Number of steps per cycle 1 2 4 8 : preset This sets the tracking servo filter data RAM to 0 when switched from track jump to servo on only when SFJP = 1 (during surf jump operation). FPS1, FPS0: Gain setting when transferring data from the focus filter to the PWM block. TPS1, TPS0: Gain setting when transferring data from the tracking filter to the PWM block. This is effective for increasing the overall gain in order to widen the servo band. Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However, 6dB, 12dB and 18dB can be selected independently for focus and tracking by setting the relative gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00. FPS1 0 0 1 1 FPS0 0 1 0 1 Relative gain 0dB +6dB +12dB +18dB TPS1 0 0 1 1 TPS0 0 1 0 1 Relative gain 0dB +6dB +12dB +18dB : preset SJHD: INBK: This holds the tracking filter output at the value when surf jump starts during surf jump. When INBK = 0 (off), the brake circuit masks the tracking drive signal with TRKCNCL which is generated by taking the MIRR signal at the TZC edge. When INBK = 1 (on), the tracking filter input is masked instead of the drive output. The tracking filter input is masked when the MIRR signal is high by setting MTI0 = 1 (on). TJD0: The counter changes once for each sampling cycle of the focus servo filter. When MCK is 128Fs, the sampling frequency is 88.2kHz. When converted to FE input, 1 step is approximately 1/29 x VDD/2, VDD = supply voltage. MTI0: - 116 - CXD3003R $3B (preset: $3B E0 50) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 0 D1 0 D0 0 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT SFOX, SFO2, SFO1: FOK slice level Default value: 011 (28/256 x VDD/2, VDD = supply voltage) RFDC input conversion SFOX 0 0 0 0 1 1 1 1 SFO2 0 0 1 1 0 0 1 1 SFO1 0 1 0 1 0 1 0 1 Slice level 16/256 x VDD/2 20/256 x VDD/2 24/256 x VDD/2 28/256 x VDD/2 32/256 x VDD/2 40/256 x VDD/2 48/256 x VDD/2 56/256 x VDD/2 : preset - 117 - CXD3003R SDF2, SDF1: DFCT slice level Default value: 10 (0.0313 x VDDV) RFDC input conversion SDF2 0 0 1 1 SDF1 0 1 0 1 Slice level 0.0156 x VDD 0.0234 x VDD 0.0313 x VDD 0.0391 x VDD : preset, VDD: supply voltage MAX2, MAX1: DFCT maximum time Default value: 00 (no timer limit) MAX2 0 0 1 1 MAX1 0 1 0 1 DFCT maximum time No timer limit 2.00ms 2.36 2.72 : preset BTF: Bottom hold double-speed count-up mode for MIRR signal generation On/off (default: off) On when set to 1. Peak hold 2 for DFCT signal generation Count-down speed setting Default value: 01 (0.086 x VDD V/ms, 44.1kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. D2V2 0 0 1 1 D2V1 0 1 0 1 Count-down speed [V/ms] 0.0431 x VDD 0.0861 x VDD 0.172 x VDD 0.344 x VDD [kHz] 22.05 44.1 88.2 176.4 D2V2, D2V1: : preset, VDD: supply voltage D1V2, D1V1: Peak hold 1 for DFCT signal generation Count-down speed setting Default value: 01 (0.688 x VDD V/ms, 352.8kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. D1V2 0 0 1 1 D1V1 0 1 0 1 Count-down speed [V/ms] 0.344 x VDD 0.688 x VDD 1.38 x VDD 2.75 x VDD [kHz] 176.4 352.8 705.6 1411.2 : preset, VDD: supply voltage RINT: This initializes the initial-state registers of the circuits which generate MIRR, DFCT and FOK. - 118 - CXD3003R $3C (preset: $3C 00 80) D15 D14 D13 D12 D11 D10 D9 D8 0 D7 D6 D5 D4 D3 0 D2 0 D1 0 D0 0 COSS COTS CETZ CETF COT2 COT1 MOT2 BTS1 BTS0 MRC1 MRC0 COSS, COTS: These select the TZC signal used when generating the COUT signal. Preset = HPTZC. COSS 1 0 0 COTS -- 0 1 TZC STZC HPTZC DTZC : preset, --: don't care STZC is the TZC generated by sampling the TE signal at 700kHz. (when MCK = 128Fs) DTZC is the delayed phase STZC. (The delay amount can be selected by D14 of $36.) HPTZC is the fast phase TZC passed through a HPF with a cut-off frequency of 1kHz. See 5-13. CETZ: The input from the TE pin normally enters the TRK filter and is used to generate the TZC signal. However, the input from the CE pin can also be used. This function is for the center error servo. When CETZ = 0, the TZC signal is generated by using the TE input signal. When CETZ = 1, the TZC signal is generated by using the CE input signal. When CETF = 0, the signal input to the TE pin is input to the TRK servo filter. When CETF = 1, the signal input to the CE pin is input to the TRK servo filter. CETF: These commands output the TZC signal. COT2, COT1: This outputs the TZC signal from the COUT pin. COT2 1 0 0 COT1 -- 1 0 COUT pin output STZC HPTZC COUT : preset, --: don't care MOT2: The STZC signal is output from the MIRR pin by setting MOT2 to 1. These commands set the MIRR signal generation circuit. BTS1, BTS0: This sets the count-up speed for the bottom hold value of the MIRR generation circuit. The time per step is approximately 708 ns (when MCK = 128Fs). The preset value is BTS1 = 1, BTS0 = 0 like the CXD2586R. However, this is valid only when BTF of $3B is 0. MRC1, MRC0: This sets the minimum pulse width for masking the MIRR signal of the MIRR generation circuit. As noted in 5-9, the MIRR signal is generated by comparing the waveform obtained by subtracting the bottom hold value from the peak hold value with the MIRR comparator level. Strictly speaking, however, for MIRR to become high, these levels must be compared continuously for a certain time. This sets that time. The preset value is MRC1 = 0, MRC0 = 0 same time as the CXD2586R. BTS1 BTS0 0 0 1 1 0 1 0 1 Number of count-up steps per cycle 1 2 4 8 MRC1 MRC0 0 0 1 1 0 1 0 1 Setting time [s] 5.669 11.338 22.675 45.351 : preset (when MCK = 128Fs) - 119 - CXD3003R $3D (preset: $3D 00 00) D15 D14 D13 D12 D11 0 D10 D9 D8 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 SFID SFSK THID THSK SFID: TLD2 TLD1 TLD0 SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK filter second-stage output. When the low frequency component of the tracking error signal obtained from the RF amplifier is attenuated, the low frequency can be amplified and input to the SLD servo filter. Only during TRK servo gain up2 operation, coefficient K30 is used instead of K00. Normally the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to M00 can be kept uniform by adjusting the K30 value even during the above switching. TRK hold filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK filter second-stage output. When signals other than the tracking error signal from the RF amplifier are input to the SE input pin, the signal transmitted from the TE pin can be obtained as TRK hold filter input. Only during TRK servo gain up2 operation, coefficient K46 is used instead of K40. Normally the DC gain between the TE input pin and M0D changes for TRK filter gain moral and gain up 2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to M18 can be kept uniform by adjusting the K46 value even during the above switching. Please refer to 5-21. Filter Composition, for further information on SFID, SFSK, THID and THSK commands. SFSK: THID: THSK: TLD0 to 2: SLD filter correction turns on and off independently of the TRK filter. Please refer also to $38 (TLC0 to 2) and Figure 5-3. TLC2 0 1 TLD2 -- 0 1 Traverse center correction TRK filter OFF ON ON SLD filter OFF ON OFF TLC1 0 1 TLD1 -- 0 1 Tracking zero level correction TRK filter OFF ON ON SLD filter OFF ON OFF TLC0 0 1 TLD0 -- 0 1 VC level correction TRK filter OFF ON ON SLD filter OFF ON OFF : preset, -- : Don't care - 120 - CXD3003R * Input coefficient inversion when SFID = 1 and THID = 1 The preset coefficients for the TRK filter are negative for input and positive for output. With this, the error input and servo that outputs reversed phase drive can be hypothesized. Negative input coefficient TE K19 TRK Filter Positive output coefficient K22 Negative input coefficient SE K00 SLD Filter Positive output coefficient K05 Positive input coefficient TRK Hold K40 TRK Hold Filter Positive output coefficient K45 When SFID = 1, the TRK filter negative input coefficient is applied to the SLD filter, so invert the SLD input coefficient (K00) code. (For example, inverting the code for coefficient K00: E0h results in 60h.) For the same reason, when THID = 1, invert the TRK hold input coefficient (K40) code. Negative input coefficient TE K19 TRK Filter M0D Positive output coefficient K22 Positive input coefficient SE K00 SLD Filter Positive output coefficient K05 Negative input coefficient TRK Hold K40 TRK Hold Filter Positive output coefficient K45 for TRK servo gain normal Please refer also to 5-21. Filter Composition. - 121 - CXD3003R $3E (preset: $3E 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 0 D4 D3 D2 D1 D0 F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD LKIN COIN MDFI MIRI XT1D F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage On when set to 1; default = 0. F1NM: Gain normal F1DM: Gain down T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage On when set to 1; default = 0. T1NM: Gain normal T1UM: Gain up F3NM, F3DM: Quasi double accuracy setting for FCS servo filter third-stage On when set to 1; default = 0. Generally, the advance amount of the phase becomes large by partially setting the FCS servo third-stage filter which is used as the phase compensation filter to double accuracy. F3NM: Gain normal F3DM: Gain down T3NM, T3UM: Quasi double accuracy setting for TRK servo filter third-stage On when set to 1; default = 0. Generally, the advance amount of the phase becomes large by partially setting the TRK servo third-stage filter which is used as the phase compensation filter to double accuracy. T3NM: Gain normal T3UM: Gain up Note) Filter first- and third-stage quasi double accuracy settings can be set individually. See "FILTER Composition" at the end of this specification concerning quasi double accuracy. DFIS: FCS hold filter input extraction node selection 0: M05 (Data RAM address 05); default 1: M04 (Data RAM address 04) This command masks the TLC2 command set by D2 of $38 only when FOK is low. On when set to 1; default = 0 When 0, the internally generated LOCK signal is output to the LOCK pin. (default) When 1, the LOCK signal can be input from an external source to the LOCK pin. When 0, the internally generated COUT signal is output to the COUT pin. (default) When 1, the COUT signal can be input from an external source to the COUT pin. The MIRR, DFCT and FOK signals can also be input from an external source. When 0, the MIRR, DFCT and FOK signals are generated internally. (default) When 1, the MIRR, DFCT and FOK signals can be input from an external source through the MIRR, DFCT and FOK pins. When 0, the MIRR signal is generated internally. (default) When 1, the MIRR signal can be input from an external source through the MIRR pin. MDFI 0 0 1 MIRI 0 1 -- MIRR, DFCT and FOK are all generated internally. MIRR only is input from an external source. MIRR, DFCT and FOK are all input from an external source. : preset, --: don't care XT1D: The clock input from FSTI can be used without being frequency-divided as the master clock for the servo block by setting D0 to 1. This command takes precedence over the XTSL pin, XT2D and XT4D. See the description of $3F for XT2D and XT4D. - 122 - TLCD: LKIN: COIN: MDFI: MIRI: CXD3003R $3F (preset: $3F 00 00) D15 0 AGG4: D14 D13 D12 D11 0 D10 D9 D8 D7 0 D6 D5 D4 D3 D2 D1 D0 0 AGG4 XT4D XT2D DRR2 DRR1 DRR0 ASFG FTQ LPAS SRO1 SRO0 AGHF This varies the amplitude of the internally generated sine wave using the AGGF and AGGT commands during AGC. When AGG4 = 0, the default is used. When AGG4 = 1, the setting is as shown in the table below. AGGF (MSB) 0 0 1 1 AGGT (LSB) 0 1 0 1 TE/FE input conversion 1/64 x VDD/2 1/32 x VDD/2 1/16 x VDD/2 1/8 x VDD/2 : preset These settings are the same for both focus auto gain control and tracking auto gain control. XT4D, XT2D: MCK (digital servo master clock) frequency division setting This command forcibly sets the frequency division ratio to 1/4, 1/2 or 1/1 when MCK is generated from the signal input to the FSTI pin. See the description of $3E for XT1D. XT1D 0 1 0 0 XT2D 0 -- 1 0 XT4D 0 -- -- 1 Frequency division ratio According to XTSL 1/1 1/2 1/4 : preset, --: don't care DRR2 to DRR0: Partially clears the Data RAM values (0 write). The following values are cleared when set to 1 (on) respectively; default = 0 DRR2: M08, M09, M0A DRR1: M00, M01, M02 DRR0: M00, M01, M02 only when LOCK = low Note) Set DRR1 and DRR0 on for 50s or more. ASFG: When vibration detection is performed during anti-shock circuit operation, FCS servo filter is forcibly set to gain normal status. On when set to 1; default = 0 LPAS: Built-in analog buffer low-current consumption mode This mode reduces the total analog buffer current consumption for the VC, TE, SE and FE input analog buffers by using a single operational amplifier. On when set to 1; default = 0 Note) When using this mode, first check whether each error signal is properly A/D converted using the SRO1 and SRO0 commands of $3F. SRO1, SRO0: These commands are used to output various data externally continuously which have been specified with the $39 command. (However, D15 (DAC) of $39 must be set to 1.) Digital output (SOCK, XOLT and SOUT) can be obtained from three specified pins by setting these commands to 1 respectively. The default is 0, 0. (no readout) The output pins for each case are shown below. SRO1 = 1 SOCK XOLT SOUT DA13 pin DA12 pin DA14 pin SRO0 = 1 DA10 pin DA09 pin DA11 pin (See "Description of Data Readout" on the following page.) AGHF: FTQ: This halves the frequency of the internally generated sine wave during AGC. The slope of the output during focus search is a quarter of the conventional output slope. - 123 - CXD3003R Description of Data Readout SOCK (5.6448MHz) XOLT (88.2kHz) *** *** *** *** SOUT MSB *** LSB MSB *** LSB 16-bit register for serial/parallel conversion SOUT LSB 16-bit register for latch LSB To the 7-segment LED * * * * * To the 7-segment LED * MSB SOCK CLK CLK MSB Data is connected to the 7-segment LED by 4-bits at a time. This enables Hex display using four 7-segment LEDs. XOLT SOUT Serial data input D/A SOCK XOLT Clock input Latch enable input Analog output Offset adjustment, gain adjustment To an oscilloscope, etc. Waveforms can be monitored with an oscilloscope using a serial input-type D/A converter as shown above. - 124 - CXD3003R 5-20. List of Servo Filter Coefficients Fix indicates that normal preset values should be used. - 125 - CXD3003R - 126 - CXD3003R 5-21. Filter Composition The internal filter composition is shown below. K and M indicate coefficient RAM and Data RAM address values respectively. FCS Servo Gain Normal fs = 88.2kHz FCS Hold Reg 2 FCS In Reg Sin ROM 2-1 DFCT K06 AGFON K06 K0F M03 Z-1 K08 K09 M04 Z-1 K0A 2-7 K0B 2-7 K0D K0C M05 Z-1 K0E FCS Hold Reg 1 M06 Z-1 K10 K11 FCS AUTO Gain M07 K13 27 FCS PWM FCS SRCH Note) Set the MSB bit of the K0B and K0D coefficients to 0. FCS Servo Gain Down fs = 88.2kHz FCS Hold Reg 2 FCS In Reg 2-1 DFCT K06 K2B M03 Z-1 K24 K25 M04 Z-1 K26 2-7 K27 2-7 K29 K28 M05 Z-1 K2A FCS Hold Reg 1 M06 Z-1 K2C K2D FCS AUTO Gain M07 K13 27 FCS PWM FCS SRCH Note) Set the MSB bit of the K27 and K29 coefficients to 0. - 127 - CXD3003R TRK Servo Gain Normal fs = 88.2kHz TRK Hold Reg TRK In Reg Sin ROM 2-1 AGTON K19 DFCT K19 To SLD Servo, TRK Hold TRK AUTO Gain K22 M0F K23 M0B Z-1 K1A M0C Z-1 K1B K1C 2-7 K1D 2-7 M0D Z-1 K1E K20 M0E Z-1 K21 27 TRK PWM TRK JMP K1F Note) Set the MSB bit of the K1D and K1F coefficients to 0. TRK Servo Gain Up 1 fs = 88.2kHz TRK Hold Reg TRK In Reg 2-1 DFCT K19 TRK AUTO Gain M0B Z-1 K1A K1B M0C Z-1 K3C K3D M0E Z-1 TRK JMP K3E M0F 27 K23 TRK PWM - 128 - CXD3003R TRK Servo Gain Up 2 fs = 88.2kHz TRK Hold Reg TRK In Reg 2-1 DFCT K19 To SLD Servo, TRK Hold TRK AUTO Gain K3E M0F K23 M0B Z-1 K36 M0C Z-1 K37 K38 2-7 K39 2-7 K3B K3A Z-1 K3C M0E Z-1 K3D 27 TRK PWM TRK JMP Note) Set the MSB bit of the K39 and K3B coefficients to 0. SLD Servo fs = 345Hz TRK SERVO FILTER Second-stage output K30 M0D 2-1 SFID K00 Z-1 K01 2-7 K02 2-7 K04 K03 Z-1 SLD MOV SFSK (only when TGUP2 is used) M00 SLD In Reg M01 K05 TRK AUTO Gain M02 2-7 K07 SLD PWM Note) Set the MSB bit of the K02 and K04 coefficients to 0. HPTZC/Auto Gain fs = 88.2kHz FCS In Reg TRK In Reg Sin ROM 2-1 AGFON 2-1 AGTON AGFON M08 Z-1 K14 K15 M09 Z-1 Slice TZC Reg M0A Z-1 K17 AUTO Gain Reg Slice - 129 - CXD3003R Anti Shock fs = 88.2kHz TRK In Reg 2-1 K12 M08 Z-1 M09 Z-1 K31 K16 2-7 M0A Z-1 K33 K35 Comp Anti Shock Reg K34 Note) Set the MSB bit of the K34 coefficient to 0. The comparator input is 1/16 the maximum amplitude of the comparator input. AVRG fs = 88.2kHz 2-1 VC, TE, FE, RFDC 2-7 M08 Z-1 AVRG Reg TRK Hold fs = 345Hz TRK SERVO FILTER Second-stage output K46 M0D 2-1 THID K40 Z-1 K41 2-7 K42 2-7 K44 K43 Z-1 THSK (only when TGUP2 is used) M18 SLD In Reg M19 K45 TRK Hold Reg Note) Set the MSB bit of the K42 and K44 coefficients to 0. FCS Hold fs = 345Hz FCS Hold Reg 1 K48 M10 Z-1 K49 2-7 K4A 2-7 M11 Z-1 K4B K4D FCS Hold Reg 2 K4C Note) Set the MSB bit of the K4A and K4C coefficients to 0. - 130 - CXD3003R FCS Servo Gain Normal; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EAXX0) FCS Hold Reg 2 FCS In Reg Sin ROM 2-1 AGFON K06 DFCT K06 K0F M03 Z-1 81H 2-7 K08 2-7 K09 K0B 7FH K0A 2-7 2-7 K0D K0E K0C M04 Z-1 M05 Z-1 80H FCS Hold Reg 1 M06 Z-1 K10 2-7 K11 FCS AUTO Gain M07 K13 27 FCS PWM FCS SRCH 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K0B and K0D coefficients during normal operation, and of the K08, K09 and K0E coefficients during quasi double accuracy to 0. FCS Servo Gain Down; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3E5XX0) FCS Hold Reg 2 FCS In Reg 2-1 DFCT K06 K2B M03 Z-1 M04 Z-1 K26 2-7 K25 K27 2-7 K29 K2A K28 M05 Z-1 FCS Hold Reg 1 M06 Z-1 K2C 2-7 K2D FCS AUTO Gain M07 K13 81H 2-7 K24 2-7 7FH 80H 27 FCS PWM FCS SRCH 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K27 and K29 coefficients during normal operation, and of the K24, K25 and K2A coefficients during quasi double accuracy to 0. - 131 - CXD3003R TRK Servo Gain Normal; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EXAX0) TRK Hold Reg TRK In Reg Sin ROM 2-1 AGTON K19 DFCT K19 TRK AUTO Gain M0B Z-1 81H 2-7 K1A 2-7 K1B K1D 7FH K1C 2-7 2-7 K1F K20 TRK JMP K1E M0C Z-1 M0D Z-1 80H 2-7 K21 27 TRK PWM M0E Z-1 K22 M0F K23 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K1D and K1F coefficients during normal operation, and of the K1A, K1B and K20 coefficients during quasi double accuracy to 0. TRK Servo Gain up 1; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0) TRK Hold Reg TRK In Reg 2-1 DFCT K19 TRK AUTO Gain M0B Z-1 M0C Z-1 M0E Z-1 TRK JMP K3D 2-7 K1B K3C K3E M0F 27 K23 TRK PWM 81H 2-7 K1A 2-7 7FH 80H 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K1A, K1B and K3C coefficients during quasi double accuracy to 0. - 132 - CXD3003R TRK Servo Gain up 2; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0) TRK Hold Reg TRK In Reg 2-1 DFCT K19 TRK AUTO Gain M0B Z-1 M0C Z-1 K38 2-7 K37 K39 2-7 K3B K3C TRK JMP K3A M0D Z-1 M0E Z-1 K3D 2-7 K3E M0F K23 81H 2-7 K36 2-7 7FH 80H 27 TRK PWM 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K39 and K3B coefficients during normal operation, and of the K36, K37 and K3C coefficients during quasi double accuracy to 0. - 133 - CXD3003R 5-22. TRACKING and FOCUS Frequency Response TRACKING frequency response 40 NORMAL GAIN UP 30 90 20 G 0 10 -90 0 180 -10 2.1 10 100 f - Frequency [Hz] 1K -180 20K FOCUS frequency response 40 NORMAL GAIN DOWN 30 90 20 180 G 0 10 -90 0 -10 2.1 10 100 f - Frequency [Hz] 1K -180 20K - 134 - - Phase [degree] G - Gain [dB] - Phase [degree] G - Gain [dB] VDD GFS GND FOK XLAT DATA PWMI SCLK CLOK XRST SENS XWO MUTE SQCK SCOR SQSO LDON SCSY LPF Circuit [6] Application Circuit LPF Circuit DFCT MIRR 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 NC NC NC FOK XTLI XLAT DIRC XWO DTS0 MIRR AO1F DFCT SCLK ATSK AO2F CLOK DATA SENS AO1R XTLO COUT AVSS3 AVSS5 AO2R DVSS4 AVDD5 AVSS4 AVDD3 DVDD4 AVDD4 DVSS3 DAS1 DAS0 DTS1 NC NC NC 72 NC 71 DTS2 70 XRST 69 SCSY 68 SQCK 67 SQSO 66 EXCK 65 SBSO 64 SCOR 63 WFCK 62 MUTE 61 DOUT 60 MD2 59 DVDD3 58 C16M 57 C4M 56 FSTO 55 NC 54 FSTI 53 MCKO 52 XTSL 51 DVSS2 50 DA01 49 DA02 48 DA03 47 DA04 46 DA05 45 DA06 44 DVDD2 43 DA07 42 DA08 41 DA09 40 DA10 39 NC 38 AVSS1 NC 37 ASYI WDCK RFAC BIAS NC PSSL BCKI DA14 ASYE PCMDI AVDD1 ASYO DVSS1 DA16 DA15 DVDD1 LRCKI DA13 DA12 DA11 NC LRCK NC XPLCK XUGF RFCK XRAOF C2PO MNT3 GND MNT0 MNT1 MNT2 MCKO C16M C4M DOUT WFCK EXCK SBSO 109 NC 110 NC 111 TESTA 112 PWMI FSW MON 115 MDP MDS 116 MDS 117 LOCK 118 SSTP 119 DVSS5 120 SFDR 121 SRDR 122 TFDR 123 TRDR 124 FFDR 125 FRDR 126 DVDD5 127 NC 128 VCOO 129 VCOI 130 TEST 131 TES2 132 TES3 PDO 133 PDO 134 VCKI 135 V16M 136 AVDD2 137 IGEN 138 AVSS2 ADIO 140 RFDC 141 CE 142 TE 143 NC 144 NC NC VPCO1 VPCO2 SE VC VCTL FILO FILI NC FE PCO CLTV 139 ADIO Driver Circuit LOCK 114 MON 113 FSW +5V SSTP SLED SPDL GND FG TD TG FD LDON VCC GND RFO FZC FE CE TE VC Driver Circuit 1 2 3 7 4 8 5 COUT 6 VC SOUT SOCK XOLT WDCK GTOP - 135 - 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXD3003R CXD3003R Package Outline Unit: mm 144PIN LQFP (PLASTIC) 22.0 0.2 20.0 0.1 108 109 73 1.7 MAX 72 B A 144 37 1 36 0.5 0.22 0.05 0.1 M S S 0 MIN 0.22 0.05 0.1 S (21.0) 0 to 10 DETAIL A 0.5 0.15 0.145 0.05 (0.2) (0.125) DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.3 g SONY CODE EIAJ CODE JEDEC CODE LQFP-144P-L01 LQFP144-P-2020-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT 144PIN LQFP(PLASTIC) 22.0 0.2 20.0 0.1 108 109 73 72 1.7 MAX B A 144 1 0.5 0.22 0.05 36 0.1 M S S 0.1 0.05 0.1 S 37 0.5 0.15 (21.0) 0.22 0.05 (0.125) (0.2) 0 to 10 DETAIL A DETAIL B 0.145 0.05 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-144P-L021 LQFP144-P-2020 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 1.3g - 136 - CXD3003R Package Outline Unit: mm 144PIN LQFP(PLASTIC) 22.0 0.2 20.0 0.1 108 109 73 72 1.7 MAX B A 144 1 0.5 0.22 0.05 36 0.1 M S S 0.1 S 37 (21.0) 0.1 0.05 0.22 0.05 (0.125) (0.2) 0 to 10 DETAIL A 0.5 0.15 DETAIL B 0.145 0.05 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-144P-L022 LQFP144-P-2020 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 / COPPER ALLOY 1.3g 144PIN LQFP(PLASTIC) 22.0 0.2 20.0 0.1 108 109 73 0.1 72 1.7 MAX 1.4 0.1 B A 144 0.5 1 0.22 0.05 36 0.08 M 37 (21.0) 0.22 0.05 (0.2) 0 to 10 DETAIL A 0.5 0.15 DETAIL B (0.15) 0.15 0.05 0.1 0.05 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-144P-L051 LQFP144-P-2020 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 1.3g - 137 - |
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